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Searched refs:dcfg (Results 1 – 14 of 14) sorted by relevance

/drivers/video/fbdev/geode/
Dvideo_cs5530.c98 u32 dcfg; in cs5530_configure_display() local
100 dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG); in cs5530_configure_display()
103 dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK in cs5530_configure_display()
110 dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT in cs5530_configure_display()
115 dcfg |= CS5530_DCFG_DAC_PWR_EN; in cs5530_configure_display()
116 dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN; in cs5530_configure_display()
120 dcfg |= CS5530_DCFG_FP_PWR_EN; in cs5530_configure_display()
121 dcfg |= CS5530_DCFG_FP_DATA_EN; in cs5530_configure_display()
126 dcfg |= CS5530_DCFG_CRT_HSYNC_POL; in cs5530_configure_display()
128 dcfg |= CS5530_DCFG_CRT_VSYNC_POL; in cs5530_configure_display()
[all …]
Dvideo_gx.c235 u32 dcfg, misc; in gx_configure_display() local
238 dcfg = read_vp(par, VP_DCFG); in gx_configure_display()
241 dcfg &= ~(VP_DCFG_VSYNC_EN | VP_DCFG_HSYNC_EN); in gx_configure_display()
242 write_vp(par, VP_DCFG, dcfg); in gx_configure_display()
245 dcfg &= ~(VP_DCFG_CRT_SYNC_SKW in gx_configure_display()
250 dcfg |= VP_DCFG_CRT_SYNC_SKW_DEFAULT; in gx_configure_display()
253 dcfg |= VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN; in gx_configure_display()
270 dcfg |= VP_DCFG_CRT_HSYNC_POL; in gx_configure_display()
272 dcfg |= VP_DCFG_CRT_VSYNC_POL; in gx_configure_display()
282 dcfg |= VP_DCFG_CRT_EN | VP_DCFG_DAC_BL_EN; in gx_configure_display()
[all …]
Ddisplay_gx.c60 u32 gcfg, dcfg; in gx_set_mode() local
68 dcfg = read_dc(par, DC_DISPLAY_CFG); in gx_set_mode()
71 dcfg &= ~DC_DISPLAY_CFG_TGEN; in gx_set_mode()
72 write_dc(par, DC_DISPLAY_CFG, dcfg); in gx_set_mode()
91 dcfg = 0; in gx_set_mode()
108 dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN | in gx_set_mode()
114 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; in gx_set_mode()
117 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; in gx_set_mode()
120 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP; in gx_set_mode()
121 dcfg |= DC_DISPLAY_CFG_PALB; in gx_set_mode()
[all …]
Dlxfb_ops.c348 unsigned int gcfg, dcfg; in lx_set_mode() local
437 dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */ in lx_set_mode()
438 dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */ in lx_set_mode()
439 dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */ in lx_set_mode()
440 dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */ in lx_set_mode()
441 dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */ in lx_set_mode()
442 dcfg |= DC_DISPLAY_CFG_VISL; in lx_set_mode()
443 dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */ in lx_set_mode()
449 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; in lx_set_mode()
453 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; in lx_set_mode()
[all …]
/drivers/nvmem/
Dsnvs_lpgpr.c35 const struct snvs_lpgpr_cfg *dcfg; member
56 const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; in snvs_lpgpr_write() local
60 ret = regmap_read(priv->regmap, dcfg->offset_hplr, &lock_reg); in snvs_lpgpr_write()
67 ret = regmap_read(priv->regmap, dcfg->offset_lplr, &lock_reg); in snvs_lpgpr_write()
74 return regmap_bulk_write(priv->regmap, dcfg->offset + offset, val, in snvs_lpgpr_write()
82 const struct snvs_lpgpr_cfg *dcfg = priv->dcfg; in snvs_lpgpr_read() local
84 return regmap_bulk_read(priv->regmap, dcfg->offset + offset, in snvs_lpgpr_read()
96 const struct snvs_lpgpr_cfg *dcfg; in snvs_lpgpr_probe() local
105 dcfg = of_device_get_match_data(dev); in snvs_lpgpr_probe()
106 if (!dcfg) in snvs_lpgpr_probe()
[all …]
/drivers/remoteproc/
Dimx_rproc.c85 const struct imx_rproc_dcfg *dcfg; member
161 const struct imx_rproc_dcfg *dcfg = priv->dcfg; in imx_rproc_start() local
165 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, in imx_rproc_start()
166 dcfg->src_mask, dcfg->src_start); in imx_rproc_start()
176 const struct imx_rproc_dcfg *dcfg = priv->dcfg; in imx_rproc_stop() local
180 ret = regmap_update_bits(priv->regmap, dcfg->src_reg, in imx_rproc_stop()
181 dcfg->src_mask, dcfg->src_stop); in imx_rproc_stop()
191 const struct imx_rproc_dcfg *dcfg = priv->dcfg; in imx_rproc_da_to_sys() local
195 for (i = 0; i < dcfg->att_size; i++) { in imx_rproc_da_to_sys()
196 const struct imx_rproc_att *att = &dcfg->att[i]; in imx_rproc_da_to_sys()
[all …]
/drivers/net/ethernet/intel/ixgbe/
Dixgbe_dcb_nl.c26 struct ixgbe_dcb_config *dcfg = &adapter->dcb_cfg; in ixgbe_copy_dcb_cfg() local
46 dst = &dcfg->tc_config[i - DCB_PG_ATTR_TC_0]; in ixgbe_copy_dcb_cfg()
95 if (dcfg->bw_percentage[tx][j] != scfg->bw_percentage[tx][j]) { in ixgbe_copy_dcb_cfg()
96 dcfg->bw_percentage[tx][j] = scfg->bw_percentage[tx][j]; in ixgbe_copy_dcb_cfg()
99 if (dcfg->bw_percentage[rx][j] != scfg->bw_percentage[rx][j]) { in ixgbe_copy_dcb_cfg()
100 dcfg->bw_percentage[rx][j] = scfg->bw_percentage[rx][j]; in ixgbe_copy_dcb_cfg()
107 if (dcfg->tc_config[j].dcb_pfc != scfg->tc_config[j].dcb_pfc) { in ixgbe_copy_dcb_cfg()
108 dcfg->tc_config[j].dcb_pfc = scfg->tc_config[j].dcb_pfc; in ixgbe_copy_dcb_cfg()
113 if (dcfg->pfc_mode_enable != scfg->pfc_mode_enable) { in ixgbe_copy_dcb_cfg()
114 dcfg->pfc_mode_enable = scfg->pfc_mode_enable; in ixgbe_copy_dcb_cfg()
/drivers/net/ethernet/atheros/
Dag71xx.c308 const struct ag71xx_dcfg *dcfg; member
349 return ag->dcfg->type == type; in ag71xx_is()
652 if (ag->dcfg->tx_hang_workaround && in ag71xx_tx_packets()
1353 skb->len & ag->dcfg->desc_pktlen_mask); in ag71xx_hard_start_xmit()
1445 pktlen_mask = ag->dcfg->desc_pktlen_mask; in ag71xx_rx_packets()
1635 const struct ag71xx_dcfg *dcfg; in ag71xx_probe() local
1653 dcfg = of_device_get_match_data(&pdev->dev); in ag71xx_probe()
1654 if (!dcfg) in ag71xx_probe()
1679 ag->dcfg = dcfg; in ag71xx_probe()
1681 memcpy(ag->fifodata, dcfg->fifodata, sizeof(ag->fifodata)); in ag71xx_probe()
[all …]
/drivers/media/pci/pt1/
Dpt1.c972 struct tc90522_config dcfg; in pt1_init_frontends() local
976 dcfg = pt1_configs[i].demod_cfg; in pt1_init_frontends()
977 dcfg.tuner_i2c = NULL; in pt1_init_frontends()
981 info->addr, &dcfg); in pt1_init_frontends()
992 tcfg.fe = dcfg.fe; in pt1_init_frontends()
994 info->type, dcfg.tuner_i2c, in pt1_init_frontends()
1001 tcfg.fe = dcfg.fe; in pt1_init_frontends()
1003 info->type, dcfg.tuner_i2c, in pt1_init_frontends()
1010 ret = pt1_init_frontend(pt1->adaps[i], dcfg.fe); in pt1_init_frontends()
/drivers/usb/dwc2/
Dgadget.c1895 u32 dcfg; in dwc2_hsotg_process_control() local
1917 dcfg = dwc2_readl(hsotg, DCFG); in dwc2_hsotg_process_control()
1918 dcfg &= ~DCFG_DEVADDR_MASK; in dwc2_hsotg_process_control()
1919 dcfg |= (le16_to_cpu(ctrl->wValue) << in dwc2_hsotg_process_control()
1921 dwc2_writel(hsotg, dcfg, DCFG); in dwc2_hsotg_process_control()
3327 u32 dcfg = 0; in dwc2_hsotg_core_init_disconnected() local
3367 dcfg |= DCFG_EPMISCNT(1); in dwc2_hsotg_core_init_disconnected()
3371 dcfg |= DCFG_DEVSPD_LS; in dwc2_hsotg_core_init_disconnected()
3375 dcfg |= DCFG_DEVSPD_FS48; in dwc2_hsotg_core_init_disconnected()
3377 dcfg |= DCFG_DEVSPD_FS; in dwc2_hsotg_core_init_disconnected()
[all …]
Dcore.h725 u32 dcfg; member
Dcore.c300 dwc2_writel(hsotg, dr->dcfg, DCFG); in dwc2_restore_essential_regs()
/drivers/media/platform/atmel/
Datmel-isc-base.c728 u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline; in isc_configure() local
735 dcfg = isc->config.dcfg_imode | in isc_configure()
749 regmap_write(regmap, ISC_DCFG, dcfg); in isc_configure()
/drivers/net/ethernet/cadence/
Dmacb_main.c3316 u32 dcfg; in macb_configure_caps() local
3324 dcfg = gem_readl(bp, DCFG1); in macb_configure_caps()
3325 if (GEM_BFEXT(IRQCOR, dcfg) == 0) in macb_configure_caps()
3327 dcfg = gem_readl(bp, DCFG2); in macb_configure_caps()
3328 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0) in macb_configure_caps()