| /drivers/clk/socfpga/ |
| D | clk-periph.c | 26 if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
27 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
61 u32 div_reg[3]; in __socfpga_periph_init() local
71 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
73 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in __socfpga_periph_init()
74 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
75 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
77 periph_clk->div_reg = NULL; in __socfpga_periph_init()
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| D | clk-periph-a10.c | 28 } else if (socfpgaclk->div_reg) { in clk_periclk_recalc_rate()
29 div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in clk_periclk_recalc_rate()
71 u32 div_reg[3]; in __socfpga_periph_init() local
81 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_periph_init()
83 periph_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_periph_init()
84 periph_clk->shift = div_reg[1]; in __socfpga_periph_init()
85 periph_clk->width = div_reg[2]; in __socfpga_periph_init()
87 periph_clk->div_reg = NULL; in __socfpga_periph_init()
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| D | clk-gate-a10.c | 29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
98 u32 div_reg[3]; in __socfpga_gate_init() local
130 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in __socfpga_gate_init()
132 socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; in __socfpga_gate_init()
133 socfpga_clk->shift = div_reg[1]; in __socfpga_gate_init()
134 socfpga_clk->width = div_reg[2]; in __socfpga_gate_init()
136 socfpga_clk->div_reg = NULL; in __socfpga_gate_init()
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| D | clk-gate-s10.c | 22 } else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
23 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
36 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_dbg_clk_recalc_rate()
72 unsigned long gate_idx, unsigned long div_reg, in s10_register_gate() argument
93 if (div_reg) in s10_register_gate()
94 socfpga_clk->div_reg = regbase + div_reg; in s10_register_gate()
96 socfpga_clk->div_reg = NULL; in s10_register_gate()
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| D | clk-gate.c | 98 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
99 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
102 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) in socfpga_clk_recalc_rate()
174 u32 div_reg[3]; in socfpga_gate_init() local
211 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); in socfpga_gate_init()
213 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; in socfpga_gate_init()
214 socfpga_clk->shift = div_reg[1]; in socfpga_gate_init()
215 socfpga_clk->width = div_reg[2]; in socfpga_gate_init()
217 socfpga_clk->div_reg = NULL; in socfpga_gate_init()
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| D | clk.h | 47 void __iomem *div_reg; member
60 void __iomem *div_reg; member
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| D | stratix10-clk.h | 55 unsigned long div_reg; member
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| D | clk-s10.c | 233 clks[i].gate_idx, clks[i].div_reg, in s10_clk_register_gate()
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| /drivers/clk/bcm/ |
| D | clk-bcm2835.c | 489 u32 div_reg; member
997 div = cprman_read(cprman, data->div_reg); in bcm2835_clock_get_rate()
1083 cprman_write(cprman, data->div_reg, div); in bcm2835_clock_set_rate()
1874 .div_reg = CM_OTPDIV,
1886 .div_reg = CM_TIMERDIV,
1897 .div_reg = CM_TSENSDIV,
1904 .div_reg = CM_TECDIV,
1913 .div_reg = CM_H264DIV,
1921 .div_reg = CM_ISPDIV,
1934 .div_reg = CM_SDCDIV,
[all …]
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| /drivers/clk/ |
| D | clk-vt8500.c | 22 void __iomem *div_reg; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
189 writel(divisor, cdev->div_reg); in vt8500_dclk_set_rate()
225 u32 en_reg, div_reg; in vtwm_device_clk_init() local
255 rc = of_property_read_u32(node, "divisor-reg", &div_reg); in vtwm_device_clk_init()
257 dev_clk->div_reg = pmc_base + div_reg; in vtwm_device_clk_init()
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| /drivers/clk/hisilicon/ |
| D | clk-hi3620.c | 226 u32 div_reg; member
242 void __iomem *div_reg; member
372 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
374 writel_relaxed(val, mclk->div_reg); in mmc_clk_set_timing()
432 mclk->div_reg = base + mmc_clk->div_reg; in hisi_register_clk_mmc()
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| /drivers/clk/samsung/ |
| D | clk-cpu.c | 69 static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask) in wait_until_divider_stable() argument
74 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
78 if (!(readl(div_reg) & mask)) in wait_until_divider_stable()
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| /drivers/clk/mediatek/ |
| D | clk-mtk.h | 183 u32 div_reg; member
194 .div_reg = _reg, \
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| D | clk-mtk.c | 276 mcd->flags, base + mcd->div_reg, mcd->div_shift, in mtk_clk_register_dividers()
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| D | clk-mt8516.c | 471 .div_reg = _reg, \
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| /drivers/clk/ingenic/ |
| D | cgu.c | 370 u32 div_reg, div; in ingenic_clk_recalc_rate() local
375 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
376 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
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| /drivers/net/ethernet/netronome/nfp/bpf/ |
| D | jit.c | 2406 static int div_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) in div_reg() function
3453 [BPF_ALU | BPF_DIV | BPF_X] = div_reg,
|