| /drivers/gpu/drm/radeon/ |
| D | rv740_dpm.c | 124 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
137 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
141 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
143 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
148 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
149 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
160 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
199 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
205 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
209 ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in rv740_populate_mclk_value()
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| D | rv730_dpm.c | 44 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
57 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
61 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
63 if (dividers.enable_post_div) in rv730_populate_sclk_value()
64 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
65 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
74 if (dividers.enable_post_div) in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
80 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
81 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
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| D | rv6xx_dpm.c | 142 struct atom_clock_dividers dividers; in rv6xx_convert_clock_to_stepping() local
145 clock, false, ÷rs); in rv6xx_convert_clock_to_stepping()
149 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
526 struct atom_clock_dividers *dividers, in rv6xx_calculate_vco_frequency() argument
529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
530 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
553 struct atom_clock_dividers dividers; in rv6xx_program_engine_spread_spectrum() local
560 …if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) == 0) { in rv6xx_program_engine_spread_spectrum()
561 vco_freq = rv6xx_calculate_vco_frequency(ref_clk, ÷rs, in rv6xx_program_engine_spread_spectrum()
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| D | rv770_dpm.c | 320 struct atom_clock_dividers *dividers, in rv770_calculate_fractional_mpll_feedback_divider() argument
332 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
333 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
402 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
410 memory_clock, false, ÷rs); in rv770_populate_mclk_value()
414 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
419 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
421 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
432 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
438 if (dividers.vco_mode) in rv770_populate_mclk_value()
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| D | cypress_dpm.c | 495 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
502 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
510 dividers.post_div = 1; in cypress_populate_mclk_value()
513 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
521 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in cypress_populate_mclk_value()
522 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
523 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); in cypress_populate_mclk_value()
526 if (dividers.vco_mode) in cypress_populate_mclk_value()
537 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
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| D | rs780_dpm.c | 79 struct atom_clock_dividers dividers; in rs780_initialize_dpm_power_state() local
84 default_state->sclk_low, false, ÷rs); in rs780_initialize_dpm_power_state()
88 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
89 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
90 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
92 if (dividers.enable_post_div) in rs780_initialize_dpm_power_state()
1035 struct atom_clock_dividers dividers; in rs780_dpm_force_performance_level() local
1046 ps->sclk_high, false, ÷rs); in rs780_dpm_force_performance_level()
1050 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1053 ps->sclk_low, false, ÷rs); in rs780_dpm_force_performance_level()
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| D | radeon_atombios.c | 2841 struct atom_clock_dividers *dividers) in radeon_atom_get_clock_dividers() argument
2848 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in radeon_atom_get_clock_dividers()
2861 dividers->post_div = args.v1.ucPostDiv; in radeon_atom_get_clock_dividers()
2862 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2863 dividers->enable_post_div = true; in radeon_atom_get_clock_dividers()
2875 dividers->post_div = args.v2.ucPostDiv; in radeon_atom_get_clock_dividers()
2876 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2877 dividers->ref_div = args.v2.ucAction; in radeon_atom_get_clock_dividers()
2879 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ? in radeon_atom_get_clock_dividers()
2881 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0; in radeon_atom_get_clock_dividers()
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| D | ni_dpm.c | 2004 struct atom_clock_dividers dividers; in ni_calculate_sclk_params() local
2018 engine_clock, false, ÷rs); in ni_calculate_sclk_params()
2022 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()
2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2030 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in ni_calculate_sclk_params()
2031 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in ni_calculate_sclk_params()
2042 u32 vco_freq = engine_clock * dividers.post_div; in ni_calculate_sclk_params()
2177 struct atom_clock_dividers dividers; in ni_populate_mclk_value() local
2184 memory_clock, strobe_mode, ÷rs); in ni_populate_mclk_value()
2192 dividers.post_div = 1; in ni_populate_mclk_value()
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| D | kv_dpm.c | 539 struct atom_clock_dividers dividers; in kv_set_divider_value() local
543 sclk, false, ÷rs); in kv_set_divider_value()
547 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
824 struct atom_clock_dividers dividers; in kv_populate_uvd_table() local
847 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
850 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
853 table->entries[i].dclk, false, ÷rs); in kv_populate_uvd_table()
856 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
897 struct atom_clock_dividers dividers; in kv_populate_vce_table() local
915 table->entries[i].evclk, false, ÷rs); in kv_populate_vce_table()
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| /drivers/gpu/drm/amd/display/modules/color/ |
| D | color_gamma.c | 287 struct dividers { struct
1075 struct dividers dividers) in scale_gamma() argument
1111 dividers.divider1); in scale_gamma()
1113 dividers.divider1); in scale_gamma()
1115 dividers.divider1); in scale_gamma()
1120 dividers.divider2); in scale_gamma()
1122 dividers.divider2); in scale_gamma()
1124 dividers.divider2); in scale_gamma()
1129 dividers.divider3); in scale_gamma()
1131 dividers.divider3); in scale_gamma()
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| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | ppatomctrl.c | 350 pp_atomctrl_clock_dividers_kong *dividers) in atomctrl_get_engine_pll_dividers_kong() argument
363 dividers->pll_post_divider = pll_parameters.ucPostDiv; in atomctrl_get_engine_pll_dividers_kong()
364 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock); in atomctrl_get_engine_pll_dividers_kong()
373 pp_atomctrl_clock_dividers_vi *dividers) in atomctrl_get_engine_pll_dividers_vi() argument
387 dividers->pll_post_divider = in atomctrl_get_engine_pll_dividers_vi()
389 dividers->real_clock = in atomctrl_get_engine_pll_dividers_vi()
392 dividers->ul_fb_div.ul_fb_div_frac = in atomctrl_get_engine_pll_dividers_vi()
394 dividers->ul_fb_div.ul_fb_div = in atomctrl_get_engine_pll_dividers_vi()
397 dividers->uc_pll_ref_div = in atomctrl_get_engine_pll_dividers_vi()
399 dividers->uc_pll_post_div = in atomctrl_get_engine_pll_dividers_vi()
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| D | ppatomctrl.h | 300 …dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
301 …dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
310 pp_atomctrl_clock_dividers_kong *dividers);
315 …dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
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| D | ppatomfwctrl.c | 248 struct pp_atomfwctrl_clock_dividers_soc15 *dividers) in pp_atomfwctrl_get_gpu_pll_dividers_vega10() argument
266 dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
267 dividers->ulDid = le32_to_cpu(pll_output->dfs_did); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
268 dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
269 dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
270 dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac); in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
271 dividers->ucPll_ss_enable = pll_output->pll_ss_enable; in pp_atomfwctrl_get_gpu_pll_dividers_vega10()
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| D | smu8_hwmgr.c | 439 pp_atomctrl_clock_dividers_kong dividers; in smu8_upload_pptable_to_smu() local
484 ÷rs); in smu8_upload_pptable_to_smu()
487 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
501 ÷rs); in smu8_upload_pptable_to_smu()
504 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
515 ÷rs); in smu8_upload_pptable_to_smu()
518 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
527 ÷rs); in smu8_upload_pptable_to_smu()
530 (uint8_t)dividers.pll_post_divider; in smu8_upload_pptable_to_smu()
541 ÷rs); in smu8_upload_pptable_to_smu()
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| D | vega10_hwmgr.c | 1489 struct pp_atomfwctrl_clock_dividers_soc15 dividers; in vega10_populate_single_lclk_level() local
1494 lclock, ÷rs), in vega10_populate_single_lclk_level()
1498 *curr_lclk_did = dividers.ulDid; in vega10_populate_single_lclk_level()
1557 struct pp_atomfwctrl_clock_dividers_soc15 dividers; in vega10_populate_single_gfx_level() local
1586 gfx_clock, ÷rs), in vega10_populate_single_gfx_level()
1592 cpu_to_le32(dividers.ulPll_fb_mult); in vega10_populate_single_gfx_level()
1594 current_gfxclk_level->SsOn = dividers.ucPll_ss_enable; in vega10_populate_single_gfx_level()
1596 cpu_to_le32(dividers.ulPll_ss_fbsmult); in vega10_populate_single_gfx_level()
1598 cpu_to_le16(dividers.usPll_ss_slew_frac); in vega10_populate_single_gfx_level()
1599 current_gfxclk_level->Did = (uint8_t)(dividers.ulDid); in vega10_populate_single_gfx_level()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atombios.c | 1016 struct atom_clock_dividers *dividers) in amdgpu_atombios_get_clock_dividers() argument
1023 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in amdgpu_atombios_get_clock_dividers()
1039 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1040 dividers->enable_post_div = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1042 dividers->enable_dithen = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1044 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); in amdgpu_atombios_get_clock_dividers()
1045 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); in amdgpu_atombios_get_clock_dividers()
1046 dividers->ref_div = args.v3.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1047 dividers->vco_mode = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1059 dividers->post_div = args.v5.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
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| D | amdgpu_atombios.h | 161 struct atom_clock_dividers *dividers);
214 struct atom_clock_dividers *dividers);
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| D | kv_dpm.c | 665 struct atom_clock_dividers dividers; in kv_set_divider_value() local
669 sclk, false, ÷rs); in kv_set_divider_value()
673 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
906 struct atom_clock_dividers dividers; in kv_populate_uvd_table() local
929 table->entries[i].vclk, false, ÷rs); in kv_populate_uvd_table()
932 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
935 table->entries[i].dclk, false, ÷rs); in kv_populate_uvd_table()
938 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
979 struct atom_clock_dividers dividers; in kv_populate_vce_table() local
997 table->entries[i].evclk, false, ÷rs); in kv_populate_vce_table()
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| /drivers/gpu/drm/amd/powerplay/smumgr/ |
| D | vegam_smumgr.c | 721 struct pp_atomctrl_clock_dividers_ai dividers; in vegam_calculate_sclk_params() local
730 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in vegam_calculate_sclk_params()
732 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()
733 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()
734 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()
735 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()
737 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()
739 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()
740 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in vegam_calculate_sclk_params()
741 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; in vegam_calculate_sclk_params()
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| D | fiji_smumgr.c | 861 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_calculate_sclk_params() local
873 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in fiji_calculate_sclk_params()
881 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()
884 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in fiji_calculate_sclk_params()
888 SPLL_REF_DIV, dividers.uc_pll_ref_div); in fiji_calculate_sclk_params()
890 SPLL_PDIV_A, dividers.uc_pll_post_div); in fiji_calculate_sclk_params()
904 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in fiji_calculate_sclk_params()
933 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in fiji_calculate_sclk_params()
1307 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_populate_smc_acpi_level() local
1338 table->ACPILevel.SclkFrequency, ÷rs); in fiji_populate_smc_acpi_level()
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| D | polaris10_smumgr.c | 846 struct pp_atomctrl_clock_dividers_ai dividers; in polaris10_calculate_sclk_params() local
855 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in polaris10_calculate_sclk_params()
857 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in polaris10_calculate_sclk_params()
858 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in polaris10_calculate_sclk_params()
859 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in polaris10_calculate_sclk_params()
860 sclk_setting->PllRange = dividers.ucSclkPllRange; in polaris10_calculate_sclk_params()
862 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in polaris10_calculate_sclk_params()
864 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()
865 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int; in polaris10_calculate_sclk_params()
866 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac; in polaris10_calculate_sclk_params()
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| D | tonga_smumgr.c | 542 pp_atomctrl_clock_dividers_vi dividers; in tonga_calculate_sclk_params() local
554 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in tonga_calculate_sclk_params()
562 reference_divider = 1 + dividers.uc_pll_ref_div; in tonga_calculate_sclk_params()
565 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in tonga_calculate_sclk_params()
569 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
571 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
585 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
611 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in tonga_calculate_sclk_params()
1180 struct pp_atomctrl_clock_dividers_vi dividers; in tonga_populate_smc_acpi_level() local
1199 table->ACPILevel.SclkFrequency, ÷rs); in tonga_populate_smc_acpi_level()
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| D | ci_smumgr.c | 299 struct pp_atomctrl_clock_dividers_vi dividers; in ci_calculate_sclk_params() local
311 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in ci_calculate_sclk_params()
319 ref_divider = 1 + dividers.uc_pll_ref_div; in ci_calculate_sclk_params()
322 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in ci_calculate_sclk_params()
326 SPLL_REF_DIV, dividers.uc_pll_ref_div); in ci_calculate_sclk_params()
328 SPLL_PDIV_A, dividers.uc_pll_post_div); in ci_calculate_sclk_params()
341 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in ci_calculate_sclk_params()
364 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; in ci_calculate_sclk_params()
1380 struct pp_atomctrl_clock_dividers_vi dividers; in ci_populate_smc_acpi_level() local
1403 table->ACPILevel.SclkFrequency, ÷rs); in ci_populate_smc_acpi_level()
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| /drivers/iio/afe/ |
| D | Kconfig | 14 that handles voltage dividers, current sense shunts and
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| /drivers/clk/ti/ |
| D | clock.h | 126 int *dividers; member
168 const int *dividers; member
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