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Searched refs:dsc_params (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_vdsc.c326 u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; in intel_dp_compute_dsc_params()
335 pipe_config->dsc_params.slice_count); in intel_dp_compute_dsc_params()
494 u8 num_vdsc_instances = (crtc_state->dsc_params.dsc_split) ? 2 : 1; in intel_configure_pps_for_dsc_encoder()
517 if (crtc_state->dsc_params.dsc_split) in intel_configure_pps_for_dsc_encoder()
521 if (crtc_state->dsc_params.dsc_split) in intel_configure_pps_for_dsc_encoder()
536 if (crtc_state->dsc_params.dsc_split) in intel_configure_pps_for_dsc_encoder()
540 if (crtc_state->dsc_params.dsc_split) in intel_configure_pps_for_dsc_encoder()
556 if (crtc_state->dsc_params.dsc_split) in intel_configure_pps_for_dsc_encoder()
560 if (crtc_state->dsc_params.dsc_split) in intel_configure_pps_for_dsc_encoder()
576 if (crtc_state->dsc_params.dsc_split) in intel_configure_pps_for_dsc_encoder()
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Dintel_dp.c2032 pipe_config->dsc_params.compressed_bpp = in intel_dp_dsc_compute_config()
2035 pipe_config->dsc_params.slice_count = in intel_dp_dsc_compute_config()
2055 pipe_config->dsc_params.compressed_bpp = min_t(u16, in intel_dp_dsc_compute_config()
2058 pipe_config->dsc_params.slice_count = dsc_dp_slice_count; in intel_dp_dsc_compute_config()
2066 if (pipe_config->dsc_params.slice_count > 1) { in intel_dp_dsc_compute_config()
2067 pipe_config->dsc_params.dsc_split = true; in intel_dp_dsc_compute_config()
2079 pipe_config->dsc_params.compressed_bpp); in intel_dp_dsc_compute_config()
2083 pipe_config->dsc_params.compression_enable = true; in intel_dp_dsc_compute_config()
2087 pipe_config->dsc_params.compressed_bpp, in intel_dp_dsc_compute_config()
2088 pipe_config->dsc_params.slice_count); in intel_dp_dsc_compute_config()
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Dintel_psr.c79 WARN_ON(crtc_state->dsc_params.compression_enable && in intel_psr2_enabled()
552 if (crtc_state->dsc_params.compression_enable) { in intel_psr2_config_valid()
Dintel_display_types.h983 } dsc_params; member
Dintel_ddi.c2141 if (crtc_state->dsc_params.compression_enable) in intel_ddi_get_power_domains()
/drivers/gpu/drm/amd/display/dc/dsc/
Drc_calc_dpi.c102 int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_parameters *dsc_params) in dscc_compute_dsc_parameters() argument
123 dsc_params->bytes_per_pixel = (uint32_t)dsc_ceil(d_bytes_per_pixel * 0x10000000); in dscc_compute_dsc_parameters()
132 dsc_params->pps = *pps; in dscc_compute_dsc_parameters()
133 …dsc_params->pps.initial_scale_value = 8 * rc.rc_model_size / (rc.rc_model_size - rc.initial_fullne… in dscc_compute_dsc_parameters()
135 copy_pps_fields(&dsc_cfg, &dsc_params->pps); in dscc_compute_dsc_parameters()
138 dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 : 64; in dscc_compute_dsc_parameters()
142 copy_pps_fields(&dsc_params->pps, &dsc_cfg); in dscc_compute_dsc_parameters()
143 dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits; in dscc_compute_dsc_parameters()
Ddscc_types.h50 int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_parameters *dsc_params…
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dsc.c35 …date_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params);
310 struct dsc_parameters dsc_params; in dsc_prepare_config() local
374 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) { in dsc_prepare_config()
379 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params); in dsc_prepare_config()
381 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel; in dsc_prepare_config()
502 …pdate_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params) in dsc_update_from_dsc_parameters() argument
506 reg_vals->pps = dsc_params->pps; in dsc_update_from_dsc_parameters()
512 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size; in dsc_update_from_dsc_parameters()
/drivers/gpu/drm/i915/
Di915_debugfs.c4531 yesno(crtc_state->dsc_params.compression_enable)); in i915_dsc_fec_support_show()