| /drivers/gpu/drm/radeon/ |
| D | trinity_dpm.c | 996 (old_rps->ecclk != new_rps->ecclk)) { in trinity_set_vce_clock()
998 if (new_rps->evclk || new_rps->ecclk) in trinity_set_vce_clock()
1002 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in trinity_set_vce_clock()
1506 u32 evclk, u32 ecclk, u16 *voltage) in trinity_get_vce_clock_voltage() argument
1513 if (((evclk == 0) && (ecclk == 0)) || in trinity_get_vce_clock_voltage()
1521 (ecclk <= table->entries[i].ecclk)) { in trinity_get_vce_clock_voltage()
1557 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in trinity_apply_state_adjust_rules()
1560 new_rps->ecclk = 0; in trinity_apply_state_adjust_rules()
1577 trinity_get_vce_clock_voltage(rdev, new_rps->evclk, new_rps->ecclk, &min_vce_voltage); in trinity_apply_state_adjust_rules()
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| D | radeon_asic.h | 698 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
750 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
788 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
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| D | si_dpm.c | 2937 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
2944 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
2952 (ecclk <= table->entries[i].ecclk)) { in si_get_vce_clock_voltage()
3009 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
3010 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3014 rps->ecclk = 0; in si_apply_state_adjust_rules()
5936 (old_rps->ecclk != new_rps->ecclk)) { in si_set_vce_clock()
5938 if (new_rps->evclk || new_rps->ecclk) in si_set_vce_clock()
5942 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); in si_set_vce_clock()
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| D | kv_dpm.c | 2157 new_rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2160 new_rps->ecclk = 0; in kv_apply_state_adjust_rules()
2224 new_rps->evclk || new_rps->ecclk; in kv_apply_state_adjust_rules()
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| D | radeon.h | 1342 u32 ecclk; member
1435 u32 ecclk; member
1526 u32 ecclk; member
1961 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
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| D | r600_dpm.c | 1109 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in r600_parse_extended_power_table()
1124 rdev->pm.dpm.vce_states[i].ecclk = in r600_parse_extended_power_table()
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| D | ni.c | 2722 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in tn_set_vce_clocks() argument
2728 ecclk, false, ÷rs); in tn_set_vce_clocks()
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| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | smu8_hwmgr.c | 79 if (clock <= ptable->entries[i].ecclk) in smu8_get_eclk_level()
87 if (clock >= ptable->entries[i].ecclk) in smu8_get_eclk_level()
536 (i < vce_table->count) ? vce_table->entries[i].ecclk : 0; in smu8_upload_pptable_to_smu()
622 clock = table->entries[level].ecclk; in smu8_init_vce_limit()
624 clock = table->entries[table->count - 1].ecclk; in smu8_init_vce_limit()
1256 ptable->entries[ptable->count - 1].ecclk; in smu8_dpm_update_vce_dpm()
1690 uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent; in smu8_read_sensor() local
1748 ecclk = vce_table->entries[vce_index].ecclk; in smu8_read_sensor()
1749 *((uint32_t *)value) = ecclk; in smu8_read_sensor()
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| D | smu10_hwmgr.h | 132 uint32_t ecclk; member
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| D | smu8_hwmgr.h | 148 uint32_t ecclk; member
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| D | smu7_hwmgr.h | 74 uint32_t ecclk; member
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| D | vega10_hwmgr.h | 102 uint32_t ecclk; member
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| D | vega20_hwmgr.h | 119 uint32_t ecclk; member
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| D | processpptables.c | 1137 vce_table->entries[i].ecclk = ((unsigned long)entry->ucECClkHigh << 16) in get_vce_clock_voltage_limit_table()
1585 …vce_state->ecclk = ((uint32_t)vce_clock_info->ucECClkHigh << 16) | le16_to_cpu(vce_clock_info->usE… in get_vce_state_table_entry()
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| /drivers/gpu/drm/amd/powerplay/inc/ |
| D | power_state.h | 181 unsigned long ecclk; member
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| D | hwmgr.h | 103 uint32_t ecclk; member
157 uint32_t ecclk; member
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_dpm.h | 64 u32 ecclk; member
173 u32 ecclk; member
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| D | kv_dpm.c | 2222 new_rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in kv_apply_state_adjust_rules()
2225 new_rps->ecclk = 0; in kv_apply_state_adjust_rules()
2289 new_rps->evclk || new_rps->ecclk; in kv_apply_state_adjust_rules()
3275 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); in kv_check_state_equal()
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| D | cik.c | 1347 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in cik_set_vce_clocks() argument
1355 ecclk, false, ÷rs); in cik_set_vce_clocks()
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| D | amdgpu_dpm.c | 516 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in amdgpu_parse_extended_power_table()
532 adev->pm.dpm.vce_states[i].ecclk = in amdgpu_parse_extended_power_table()
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| D | vi.c | 796 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in vi_set_vce_clocks() argument
820 ecclk, false, ÷rs); in vi_set_vce_clocks()
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| D | si_dpm.c | 3036 u32 evclk, u32 ecclk, u16 *voltage) in si_get_vce_clock_voltage() argument
3043 if (((evclk == 0) && (ecclk == 0)) || in si_get_vce_clock_voltage()
3051 (ecclk <= table->entries[i].ecclk)) { in si_get_vce_clock_voltage()
3468 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; in si_apply_state_adjust_rules()
3469 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, in si_apply_state_adjust_rules()
3473 rps->ecclk = 0; in si_apply_state_adjust_rules()
7978 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); in si_check_state_equal()
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| D | nv.c | 338 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in nv_set_vce_clocks() argument
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| D | amdgpu.h | 561 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
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| /drivers/gpu/drm/amd/include/ |
| D | kgd_pp_interface.h | 32 u32 ecclk; member
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