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Searched refs:edp_write (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/msm/edp/
Dedp_phy.c41 edp_write(phy->base + REG_EDP_PHY_CTRL, in msm_edp_phy_ctrl()
46 edp_write(phy->base + REG_EDP_PHY_CTRL, 0x000); in msm_edp_phy_ctrl()
47 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0x3f); in msm_edp_phy_ctrl()
48 edp_write(phy->base + REG_EDP_PHY_GLB_CFG, 0x1); in msm_edp_phy_ctrl()
50 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0xc0); in msm_edp_phy_ctrl()
57 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, 0x3); in msm_edp_phy_vm_pe_init()
58 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, 0x64); in msm_edp_phy_vm_pe_init()
59 edp_write(phy->base + REG_EDP_PHY_GLB_MISC9, 0x6c); in msm_edp_phy_vm_pe_init()
64 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, v0); in msm_edp_phy_vm_pe_cfg()
65 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, v1); in msm_edp_phy_vm_pe_cfg()
[all …]
Dedp_aux.c67 edp_write(aux->base + REG_EDP_AUX_DATA, reg); in edp_msg_fifo_tx()
75 edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, reg); in edp_msg_fifo_tx()
87 edp_write(aux->base + REG_EDP_AUX_DATA, in edp_msg_fifo_rx()
151 edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0); in edp_aux_transfer()
229 edp_write(aux->base + REG_EDP_AUX_TRANS_CTRL, 0); in msm_edp_aux_irq()
251 edp_write(aux->base + REG_EDP_AUX_CTRL, data); in msm_edp_aux_ctrl()
258 edp_write(aux->base + REG_EDP_AUX_CTRL, data); in msm_edp_aux_ctrl()
261 edp_write(aux->base + REG_EDP_AUX_CTRL, data); in msm_edp_aux_ctrl()
Dedp_ctrl.c391 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, EDP_INTR_MASK1); in edp_ctrl_irq_enable()
392 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, EDP_INTR_MASK2); in edp_ctrl_irq_enable()
394 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, 0x0); in edp_ctrl_irq_enable()
395 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, 0x0); in edp_ctrl_irq_enable()
457 edp_write(ctrl->base + REG_EDP_CONFIGURATION_CTRL, data); in edp_config_ctrl()
462 edp_write(ctrl->base + REG_EDP_STATE_CTRL, state); in edp_state_ctrl()
839 edp_write(ctrl->base + REG_EDP_MISC1_MISC0, data); in edp_clock_synchrous()
856 edp_write(ctrl->base + REG_EDP_SOFTWARE_MVID, m * m_multi); in edp_sw_mvid_nvid()
857 edp_write(ctrl->base + REG_EDP_SOFTWARE_NVID, n * n_multi); in edp_sw_mvid_nvid()
866 edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, EDP_MAINLINK_CTRL_RESET); in edp_mainlink_ctrl()
[all …]
Dedp.h19 #define edp_write(offset, data) msm_writel((data), (offset)) macro