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Searched refs:enable_count (Results 1 – 16 of 16) sorted by relevance

/drivers/devfreq/
Ddevfreq-event.c46 && edev->enable_count == 0) { in devfreq_event_enable_edev()
51 edev->enable_count++; in devfreq_event_enable_edev()
77 if (edev->enable_count <= 0) { in devfreq_event_disable_edev()
84 && edev->enable_count == 1) { in devfreq_event_disable_edev()
89 edev->enable_count--; in devfreq_event_disable_edev()
115 if (edev->enable_count > 0) in devfreq_event_is_enabled()
324 edev->enable_count = 0; in devfreq_event_add_edev()
358 WARN_ON(edev->enable_count); in devfreq_event_remove_edev()
457 return sprintf(buf, "%d\n", edev->enable_count); in enable_count_show()
459 static DEVICE_ATTR_RO(enable_count);
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_core_irq.c74 int ret = 0, enable_count; in _dpu_core_irq_enable() local
88 enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); in _dpu_core_irq_enable()
89 DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); in _dpu_core_irq_enable()
90 trace_dpu_core_irq_enable_idx(irq_idx, enable_count); in _dpu_core_irq_enable()
139 int ret = 0, enable_count; in _dpu_core_irq_disable() local
151 enable_count = atomic_read(&dpu_kms->irq_obj.enable_counts[irq_idx]); in _dpu_core_irq_disable()
152 DRM_DEBUG_KMS("irq_idx=%d enable_count=%d\n", irq_idx, enable_count); in _dpu_core_irq_disable()
153 trace_dpu_core_irq_disable_idx(irq_idx, enable_count); in _dpu_core_irq_disable()
312 int i, irq_count, enable_count, cb_count; in dpu_debugfs_core_irq_show() local
321 enable_count = atomic_read(&irq_obj->enable_counts[i]); in dpu_debugfs_core_irq_show()
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Ddpu_trace.h885 TP_PROTO(int irq_idx, int enable_count),
886 TP_ARGS(irq_idx, enable_count),
889 __field( int, enable_count )
893 __entry->enable_count = enable_count;
896 __entry->enable_count)
899 TP_PROTO(int irq_idx, int enable_count),
900 TP_ARGS(irq_idx, enable_count)
903 TP_PROTO(int irq_idx, int enable_count),
904 TP_ARGS(irq_idx, enable_count)
/drivers/gpu/drm/i915/
Di915_pmu.c603 BUILD_BUG_ON(ARRAY_SIZE(pmu->enable_count) != I915_PMU_MASK_BITS); in i915_pmu_enable()
604 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count)); in i915_pmu_enable()
605 GEM_BUG_ON(pmu->enable_count[bit] == ~0); in i915_pmu_enable()
607 pmu->enable_count[bit]++; in i915_pmu_enable()
626 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) != in i915_pmu_enable()
630 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count)); in i915_pmu_enable()
632 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0); in i915_pmu_enable()
635 engine->pmu.enable_count[sample]++; in i915_pmu_enable()
666 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count)); in i915_pmu_disable()
668 GEM_BUG_ON(engine->pmu.enable_count[sample] == 0); in i915_pmu_disable()
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Di915_pmu.h85 unsigned int enable_count[I915_PMU_MASK_BITS]; member
/drivers/clocksource/
Dsh_tmu.c45 unsigned int enable_count; member
170 if (ch->enable_count++ > 0) in sh_tmu_enable()
193 if (WARN_ON(ch->enable_count == 0)) in sh_tmu_disable()
196 if (--ch->enable_count > 0) in sh_tmu_disable()
289 if (--ch->enable_count == 0) { in sh_tmu_clocksource_suspend()
302 if (ch->enable_count++ == 0) { in sh_tmu_clocksource_resume()
469 ch->enable_count = 0; in sh_tmu_channel_setup()
/drivers/pwm/
Dpwm-imx-tpm.c67 u32 enable_count; member
278 if (++tpm->enable_count == 1) in pwm_imx_tpm_apply_hw()
281 if (--tpm->enable_count == 0) in pwm_imx_tpm_apply_hw()
405 if (tpm->enable_count > 0) in pwm_imx_tpm_suspend()
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_kms.h68 int enable_count; member
172 WARN_ON(mdp5_kms->enable_count <= 0); in mdp5_write()
178 WARN_ON(mdp5_kms->enable_count <= 0); in mdp5_read()
Dmdp5_kms.c314 mdp5_kms->enable_count--; in mdp5_disable()
315 WARN_ON(mdp5_kms->enable_count < 0); in mdp5_disable()
330 mdp5_kms->enable_count++; in mdp5_enable()
/drivers/net/dsa/mv88e6xxx/
Dhwtstamp.c152 chip->enable_count += 1; in mv88e6xxx_set_hwtstamp_config()
153 if (chip->enable_count == 1 && ptp_ops->global_enable) in mv88e6xxx_set_hwtstamp_config()
160 chip->enable_count -= 1; in mv88e6xxx_set_hwtstamp_config()
161 if (chip->enable_count == 0 && ptp_ops->global_disable) in mv88e6xxx_set_hwtstamp_config()
Dchip.h311 u16 enable_count; member
/drivers/acpi/
Ddevice_pm.c760 if (wakeup->enable_count >= max_count) in __acpi_device_wakeup_enable()
763 if (wakeup->enable_count > 0) in __acpi_device_wakeup_enable()
781 wakeup->enable_count++; in __acpi_device_wakeup_enable()
820 if (!wakeup->enable_count) in acpi_device_wakeup_disable()
826 wakeup->enable_count--; in acpi_device_wakeup_disable()
/drivers/regulator/
Dinternal.h41 unsigned int enable_count; member
Dcore.c78 u32 enable_count; /* a number of enabled shared GPIO */ member
758 if (regulator->enable_count) in regulator_total_uA_show()
934 if (sibling->enable_count) in drms_uA_update()
2047 WARN_ON(regulator->enable_count); in _regulator_put()
2290 if (pin->enable_count == 0) in regulator_ena_gpio_ctrl()
2293 pin->enable_count++; in regulator_ena_gpio_ctrl()
2295 if (pin->enable_count > 1) { in regulator_ena_gpio_ctrl()
2296 pin->enable_count--; in regulator_ena_gpio_ctrl()
2301 if (pin->enable_count <= 1) { in regulator_ena_gpio_ctrl()
2303 pin->enable_count = 0; in regulator_ena_gpio_ctrl()
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/drivers/clk/
Dclk.c77 unsigned int enable_count; member
232 return core->enable_count; in clk_core_is_enabled()
468 return !clk ? 0 : clk->core->enable_count; in __clk_get_enable_count()
828 WARN(core->enable_count > 0, "Unpreparing enabled %s\n", core->name); in clk_core_unprepare()
956 if (WARN(core->enable_count == 0, "%s already disabled\n", core->name)) in clk_core_disable()
959 if (WARN(core->enable_count == 1 && core->flags & CLK_IS_CRITICAL, in clk_core_disable()
963 if (--core->enable_count > 0) in clk_core_disable()
1019 if (core->enable_count == 0) { in clk_core_enable()
1038 core->enable_count++; in clk_core_enable()
1068 if (core->enable_count) in clk_gate_restore_context()
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/drivers/gpu/drm/i915/gt/
Dintel_engine_types.h378 unsigned int enable_count[I915_ENGINE_SAMPLE_COUNT]; member