Searched refs:fclk_khz (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 161 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()
172 new_clocks->fclk_khz = debug->force_fclk_khz; in rv1_update_clocks()
174 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) { in rv1_update_clocks()
175 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz; in rv1_update_clocks()
199 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000); in rv1_update_clocks()
219 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000); in rv1_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 327 int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000; in dcn2_update_clocks_fpga()
354 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) { in dcn2_update_clocks_fpga()
355 clk_mgr->clks.fclk_khz = fclk_adj; in dcn2_update_clocks_fpga()
366 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) in dcn2_update_clocks_fpga()
367 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; in dcn2_update_clocks_fpga()
368 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) in dcn2_update_clocks_fpga()
369 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; in dcn2_update_clocks_fpga()
372 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz; in dcn2_update_clocks_fpga()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_debug.c | 358 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
366 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
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| D | dc.c | 2487 info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz; in get_clock_requirements_for_state()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc.h | 263 int fclk_khz; member
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer_debug.c | 479 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_get_clock_states()
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| D | dcn10_hw_sequencer.c | 416 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_log_hw_state()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 1129 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / in dcn_validate_bandwidth()
1132 context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32); in dcn_validate_bandwidth()
1398 dc, DM_PP_CLOCK_TYPE_MEMORY_CLK, clocks->fclk_khz); in dcn_find_dcfclk_suits_all()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 2640 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; in dcn20_calculate_dlg_params()
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