Searched refs:fp1 (Results 1 – 13 of 13) sorted by relevance
| /drivers/gpu/drm/gma500/ |
| D | oaktrail_device.c | 201 p->fp1 = PSB_RVDC32(MRST_FPA1); in oaktrail_save_display_registers()
316 PSB_WVDC32(p->fp1, MRST_FPA1); in oaktrail_restore_display_registers()
456 .fp1 = MRST_FPA1,
480 .fp1 = FPB1,
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| D | psb_device.c | 253 .fp1 = FPA1,
277 .fp1 = FPB1,
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| D | gma_display.c | 543 crtc_state->saveFP1 = REG_READ(map->fp1); in gma_crtc_save()
592 REG_WRITE(map->fp1, crtc_state->saveFP1); in gma_crtc_restore()
593 REG_READ(map->fp1); in gma_crtc_restore()
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| D | psb_intel_display.c | 315 fp = REG_READ(map->fp1); in psb_intel_crtc_clock_get()
324 fp = p->fp1; in psb_intel_crtc_clock_get()
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| D | cdv_device.c | 518 .fp1 = FPA1,
543 .fp1 = FPB1,
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| D | psb_drv.h | 266 u32 fp1; member
300 u32 fp1; member
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| D | cdv_intel_display.c | 857 fp = REG_READ(map->fp1); in cdv_intel_crtc_clock_get()
865 fp = p->fp1; in cdv_intel_crtc_clock_get()
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| D | mdfld_device.c | 440 .fp1 = MRST_FPA1,
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| /drivers/video/fbdev/intelfb/ |
| D | intelfbhw.c | 1045 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1062 fp1 = &hw->fpb1; in intelfbhw_mode_to_hw()
1074 fp1 = &hw->fpa1; in intelfbhw_mode_to_hw()
1146 *fp1 = *fp0; in intelfbhw_mode_to_hw()
1281 const u32 *dpll, *fp0, *fp1, *pipe_conf; in intelfbhw_program_mode() local
1305 fp1 = &hw->fpb1; in intelfbhw_program_mode()
1329 fp1 = &hw->fpa1; in intelfbhw_program_mode()
1404 OUTREG(fp1_reg, *fp1); in intelfbhw_program_mode()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 173 u32 fp1; member
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| D | intel_dpll_mgr.c | 383 hw_state->fp1 = I915_READ(PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
396 I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1); in ibx_pch_dpll_prepare()
491 hw_state->fp1); in ibx_dump_hw_state()
3654 hw_state->fp1); in intel_dpll_dump_hw_state()
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| D | intel_display.c | 6914 I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
7584 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
7586 crtc_state->dpll_hw_state.fp1 = fp; in i9xx_update_pll_dividers()
8853 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
9630 crtc_state->dpll_hw_state.fp1 = fp2; in ironlake_compute_dpll()
11299 fp = pipe_config->dpll_hw_state.fp1; in i9xx_crtc_clock_get()
12798 PIPE_CONF_CHECK_X(dpll_hw_state.fp1); in intel_pipe_config_compare()
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| /drivers/gpu/drm/i915/ |
| D | i915_debugfs.c | 2843 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); in i915_shared_dplls_info()
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