Searched refs:gfx9 (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubp.c | 149 NUM_PIPES, log_2(info->gfx9.num_pipes), in hubp1_program_tiling()
150 NUM_BANKS, log_2(info->gfx9.num_banks), in hubp1_program_tiling()
151 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, in hubp1_program_tiling()
152 NUM_SE, log_2(info->gfx9.num_shader_engines), in hubp1_program_tiling()
153 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se), in hubp1_program_tiling()
154 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); in hubp1_program_tiling()
157 SW_MODE, info->gfx9.swizzle, in hubp1_program_tiling()
158 META_LINEAR, info->gfx9.meta_linear, in hubp1_program_tiling()
159 RB_ALIGNED, info->gfx9.rb_aligned, in hubp1_program_tiling()
160 PIPE_ALIGNED, info->gfx9.pipe_aligned); in hubp1_program_tiling()
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| D | dcn10_resource.c | 1211 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn10_get_default_swizzle_mode()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_mem_input.c | 360 GRPH_SW_MODE, info->gfx9.swizzle, in program_tiling()
361 GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), in program_tiling()
362 GRPH_NUM_SHADER_ENGINES, log_2(info->gfx9.num_shader_engines), in program_tiling()
363 GRPH_NUM_PIPES, log_2(info->gfx9.num_pipes), in program_tiling()
365 GRPH_SE_ENABLE, info->gfx9.shaderEnable); in program_tiling()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_debug.c | 171 plane_state->tiling_info.gfx9.swizzle); in pre_surface_trace()
257 update->plane_info->tiling_info.gfx9.swizzle); in update_surface_trace()
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| D | dc.c | 1427 if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { in get_plane_info_update_type()
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| D | dc_resource.c | 2062 pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) { in dc_validate_global_state()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubp.c | 311 NUM_PIPES, log_2(info->gfx9.num_pipes), in hubp2_program_tiling()
312 PIPE_INTERLEAVE, info->gfx9.pipe_interleave, in hubp2_program_tiling()
313 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags)); in hubp2_program_tiling()
316 SW_MODE, info->gfx9.swizzle, in hubp2_program_tiling()
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| D | dcn20_resource.c | 2019 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle); in dcn20_populate_dml_pipes_from_context()
2020 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle, in dcn20_populate_dml_pipes_from_context()
2889 plane_state->tiling_info.gfx9.swizzle = swizzle; in dcn20_get_default_swizzle_mode()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_hw_types.h | 393 } gfx9; member
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 2725 input.swizzle_mode = tiling_info->gfx9.swizzle; in fill_plane_dcc_attributes()
2854 tiling_info->gfx9.num_pipes = in fill_plane_buffer_attributes()
2856 tiling_info->gfx9.num_banks = in fill_plane_buffer_attributes()
2858 tiling_info->gfx9.pipe_interleave = in fill_plane_buffer_attributes()
2860 tiling_info->gfx9.num_shader_engines = in fill_plane_buffer_attributes()
2862 tiling_info->gfx9.max_compressed_frags = in fill_plane_buffer_attributes()
2864 tiling_info->gfx9.num_rb_per_se = in fill_plane_buffer_attributes()
2866 tiling_info->gfx9.swizzle = in fill_plane_buffer_attributes()
2868 tiling_info->gfx9.shaderEnable = 1; in fill_plane_buffer_attributes()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 334 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
343 …input->src.macro_tile_size = swizzle_mode_to_macro_tile_size(pipe->plane_state->tiling_info.gfx9.s… in pipe_ctx_to_e2e_pipe_params()
982 pipe->plane_state->tiling_info.gfx9.swizzle); in dcn_validate_bandwidth()
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