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Searched refs:hhi (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/meson/
Dmeson_vclk.c140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
141 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
204 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
208 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
211 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
213 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
215 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
219 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
221 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
223 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
[all …]
Dmeson_dw_hdmi.c304 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x333d3282); in meson_hdmi_phy_setup_mode()
305 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2136315b); in meson_hdmi_phy_setup_mode()
308 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303382); in meson_hdmi_phy_setup_mode()
309 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2036315b); in meson_hdmi_phy_setup_mode()
312 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303362); in meson_hdmi_phy_setup_mode()
313 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2016315b); in meson_hdmi_phy_setup_mode()
316 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33604142); in meson_hdmi_phy_setup_mode()
317 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x0016315b); in meson_hdmi_phy_setup_mode()
323 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33353245); in meson_hdmi_phy_setup_mode()
324 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2100115b); in meson_hdmi_phy_setup_mode()
[all …]
Dmeson_venc_cvbs.c172 regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); in meson_venc_cvbs_encoder_disable()
173 regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); in meson_venc_cvbs_encoder_disable()
175 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); in meson_venc_cvbs_encoder_disable()
176 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); in meson_venc_cvbs_encoder_disable()
191 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1); in meson_venc_cvbs_encoder_enable()
192 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); in meson_venc_cvbs_encoder_enable()
195 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001); in meson_venc_cvbs_encoder_enable()
196 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); in meson_venc_cvbs_encoder_enable()
198 regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001); in meson_venc_cvbs_encoder_enable()
199 regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); in meson_venc_cvbs_encoder_enable()
Dmeson_drv.c235 priv->hhi = devm_regmap_init_mmio(dev, regs, in meson_drv_bind_master()
237 if (IS_ERR(priv->hhi)) { in meson_drv_bind_master()
239 ret = PTR_ERR(priv->hhi); in meson_drv_bind_master()
Dmeson_venc.c1750 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); in meson_venc_enable_vsync()
1755 regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); in meson_venc_disable_vsync()
1763 regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); in meson_venc_init()
1764 regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8); in meson_venc_init()
1766 regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); in meson_venc_init()
1767 regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); in meson_venc_init()
1774 regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); in meson_venc_init()
Dmeson_drv.h31 struct regmap *hhi; member