| /drivers/video/fbdev/geode/ |
| D | video_cs5530.c | 137 int blank, hsync, vsync; in cs5530_blank_display() local
141 blank = 0; hsync = 1; vsync = 1; in cs5530_blank_display()
144 blank = 1; hsync = 1; vsync = 1; in cs5530_blank_display()
147 blank = 1; hsync = 1; vsync = 0; in cs5530_blank_display()
150 blank = 1; hsync = 0; vsync = 1; in cs5530_blank_display()
153 blank = 1; hsync = 0; vsync = 0; in cs5530_blank_display()
168 if (hsync) in cs5530_blank_display()
176 if (hsync && vsync) in cs5530_blank_display()
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| D | video_gx.c | 298 int blank, hsync, vsync, crt; in gx_blank_display() local
303 blank = 0; hsync = 1; vsync = 1; crt = 1; in gx_blank_display()
306 blank = 1; hsync = 1; vsync = 1; crt = 1; in gx_blank_display()
309 blank = 1; hsync = 1; vsync = 0; crt = 1; in gx_blank_display()
312 blank = 1; hsync = 0; vsync = 1; crt = 1; in gx_blank_display()
315 blank = 1; hsync = 0; vsync = 0; crt = 0; in gx_blank_display()
325 if (hsync) in gx_blank_display()
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| D | lxfb_ops.c | 525 int blank, hsync, vsync; in lx_blank_display() local
530 blank = 0; hsync = 1; vsync = 1; in lx_blank_display()
533 blank = 1; hsync = 1; vsync = 1; in lx_blank_display()
536 blank = 1; hsync = 1; vsync = 0; in lx_blank_display()
539 blank = 1; hsync = 0; vsync = 1; in lx_blank_display()
542 blank = 1; hsync = 0; vsync = 0; in lx_blank_display()
553 if (hsync) in lx_blank_display()
562 if (vsync && hsync) in lx_blank_display()
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| /drivers/media/v4l2-core/ |
| D | v4l2-dv-timings.c | 258 t1->bt.hsync == t2->bt.hsync && in v4l2_match_dv_timings()
306 bt->hsync, bt->hbackporch); in v4l2_print_dv_timings()
476 int v_fp, v_bp, h_fp, h_bp, hsync; in v4l2_detect_cvt() local
579 hsync = CVT_RB_H_SYNC; in v4l2_detect_cvt()
580 h_fp = h_blank - h_bp - hsync; in v4l2_detect_cvt()
601 hsync = frame_width * CVT_HSYNC_PERCENT / 100; in v4l2_detect_cvt()
602 hsync = (hsync / CVT_CELL_GRAN) * CVT_CELL_GRAN; in v4l2_detect_cvt()
603 h_fp = h_blank - hsync - h_bp; in v4l2_detect_cvt()
612 fmt->bt.hsync = hsync; in v4l2_detect_cvt()
614 fmt->bt.hbackporch = frame_width - image_width - h_fp - hsync; in v4l2_detect_cvt()
[all …]
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| /drivers/video/fbdev/core/ |
| D | fbcvt.c | 47 u32 hsync; member
127 u32 hsync; in fb_cvt_hsync() local
130 hsync = 32; in fb_cvt_hsync()
132 hsync = (FB_CVT_CELLSIZE * cvt->htotal)/100; in fb_cvt_hsync()
134 hsync &= ~(FB_CVT_CELLSIZE - 1); in fb_cvt_hsync()
135 return hsync; in fb_cvt_hsync()
277 mode->hsync_len = cvt->hsync; in fb_cvt_convert_to_mode()
366 cvt.hsync = fb_cvt_hsync(&cvt); in fb_find_mode_cvt()
370 cvt.h_front_porch = cvt.hblank - cvt.hsync - cvt.h_back_porch + in fb_find_mode_cvt()
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| /drivers/gpu/drm/gma500/ |
| D | psb_intel_display.c | 265 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in psb_intel_crtc_mode_set()
380 int hsync; in psb_intel_crtc_mode_get() local
389 hsync = REG_READ(map->hsync); in psb_intel_crtc_mode_get()
395 hsync = p->hsync; in psb_intel_crtc_mode_get()
407 mode->hsync_start = (hsync & 0xffff) + 1; in psb_intel_crtc_mode_get()
408 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; in psb_intel_crtc_mode_get()
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| D | mdfld_device.c | 192 pipe->hsync = PSB_RVDC32(map->hsync); in mdfld_save_display_registers()
318 PSB_WVDC32(pipe->hsync, map->hsync); in mdfld_restore_display_registers()
447 .hsync = HSYNC_A,
469 .hsync = HSYNC_B,
492 .hsync = HSYNC_C,
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| D | cdv_intel_display.c | 791 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in cdv_intel_crtc_mode_set()
928 int hsync; in cdv_intel_crtc_mode_get() local
934 hsync = REG_READ(map->hsync); in cdv_intel_crtc_mode_get()
940 hsync = p->hsync; in cdv_intel_crtc_mode_get()
952 mode->hsync_start = (hsync & 0xffff) + 1; in cdv_intel_crtc_mode_get()
953 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
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| D | oaktrail_device.c | 205 p->hsync = PSB_RVDC32(HSYNC_A); in oaktrail_save_display_registers()
325 PSB_WVDC32(p->hsync, HSYNC_A); in oaktrail_restore_display_registers()
463 .hsync = HSYNC_A,
487 .hsync = HSYNC_B,
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| D | psb_device.c | 260 .hsync = HSYNC_A,
284 .hsync = HSYNC_B,
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| D | cdv_device.c | 526 .hsync = HSYNC_A,
551 .hsync = HSYNC_B,
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| /drivers/media/i2c/ |
| D | ths8200.c | 225 ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync); in ths8200_setup()
236 (bt->hbackporch + bt->hsync) & 0xff); in ths8200_setup()
244 ((bt->hbackporch + bt->hsync) & 0x100) >> 1); in ths8200_setup()
302 ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff); in ths8200_setup()
304 (bt->hsync >> 2) & 0xc0); in ths8200_setup()
358 bt->hsync, bt->vsync); in ths8200_setup()
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| /drivers/gpu/drm/sun4i/ |
| D | sun4i_rgb.c | 65 u32 hsync = mode->hsync_end - mode->hsync_start; in sun4i_rgb_mode_valid() local
73 if (hsync < 1) in sun4i_rgb_mode_valid()
76 if (hsync > 0x3ff) in sun4i_rgb_mode_valid()
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| D | sun4i_tcon.c | 485 unsigned int bp, hsync, vsync; in sun4i_tcon0_mode_set_rgb() local
531 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_rgb()
533 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); in sun4i_tcon0_mode_set_rgb()
536 SUN4I_TCON0_BASIC3_H_SYNC(hsync)); in sun4i_tcon0_mode_set_rgb()
587 unsigned int bp, hsync, vsync, vtotal; in sun4i_tcon1_mode_set() local
661 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; in sun4i_tcon1_mode_set()
663 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); in sun4i_tcon1_mode_set()
666 SUN4I_TCON1_BASIC5_H_SYNC(hsync)); in sun4i_tcon1_mode_set()
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | dacnv50.c | 67 bool data, bool vsync, bool hsync) in nv50_dac_power() argument
75 0x00000001 * ! hsync) << shift; in nv50_dac_power()
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| D | sornv50.c | 48 bool data, bool vsync, bool hsync) in nv50_sor_power() argument
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| D | piornv50.c | 59 bool data, bool vsync, bool hsync) in nv50_pior_power() argument
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| /drivers/gpu/drm/i915/display/ |
| D | vlv_dsi.c | 1042 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; in bxt_dsi_get_pipe_config() local
1084 hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); in bxt_dsi_get_pipe_config()
1090 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1097 hsync *= 2; in bxt_dsi_get_pipe_config()
1106 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; in bxt_dsi_get_pipe_config()
1108 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1236 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; in set_dsi_timings() local
1240 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; in set_dsi_timings()
1248 hsync /= 2; in set_dsi_timings()
1260 hsync = txbyteclkhs(hsync, bpp, lane_count, in set_dsi_timings()
[all …]
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| /drivers/gpu/drm/mediatek/ |
| D | mtk_dpi.c | 420 struct mtk_dpi_sync_param hsync; in mtk_dpi_set_display_mode() local
458 hsync.sync_width = vm.hsync_len; in mtk_dpi_set_display_mode()
459 hsync.back_porch = vm.hback_porch; in mtk_dpi_set_display_mode()
460 hsync.front_porch = vm.hfront_porch; in mtk_dpi_set_display_mode()
461 hsync.shift_half_line = false; in mtk_dpi_set_display_mode()
485 mtk_dpi_config_hsync(dpi, &hsync); in mtk_dpi_set_display_mode()
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| /drivers/gpu/drm/ |
| D | drm_modes.c | 395 int hsync, hfront_porch, vodd_front_porch_lines; in drm_gtf_mode_complex() local
500 hsync = H_SYNC_PERCENT * total_pixels / 100; in drm_gtf_mode_complex()
501 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; in drm_gtf_mode_complex()
502 hsync = hsync * GTF_CELL_GRAN; in drm_gtf_mode_complex()
504 hfront_porch = hblank / 2 - hsync; in drm_gtf_mode_complex()
511 drm_mode->hsync_end = drm_mode->hsync_start + hsync; in drm_gtf_mode_complex()
761 if (mode->hsync) in drm_mode_hsync()
762 return mode->hsync; in drm_mode_hsync()
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| /drivers/gpu/drm/sti/ |
| D | sti_vtg.c | 117 u32 hsync; member
212 sync->hsync = (stop << 16) | start; in vtg_set_hsync_vsync_pos()
268 writel(sync[i].hsync, in vtg_set_mode()
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| /drivers/staging/media/soc_camera/ |
| D | soc_mediabus.c | 482 bool hsync = true, vsync = true, pclk, data, mode; in soc_mbus_config_compatible() local
489 hsync = common_flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH | in soc_mbus_config_compatible()
500 return (!hsync || !vsync || !pclk || !data || !mode) ? in soc_mbus_config_compatible()
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| /drivers/video/fbdev/ |
| D | pxa168fb.h | 380 #define CFG_INV_HSYNC(hsync) ((hsync) << 2) argument
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| D | atafb.c | 838 int right, hsync, left; /* standard timing in clock cycles, not pixel */ member
1060 hsync_len = pclock->hsync / plen; in falcon_decode_var()
1090 if ((plen * xres + f25.right + f25.hsync + f25.left) * in falcon_decode_var()
1093 else if ((plen * xres + f32.right + f32.hsync + in falcon_decode_var()
1096 else if ((plen * xres + fext.right + fext.hsync + in falcon_decode_var()
1105 hsync_len = pclock->hsync / plen; in falcon_decode_var()
1770 f25.hsync = h_syncs[mon_type] / f25.t; in falcon_detect()
1771 f32.hsync = h_syncs[mon_type] / f32.t; in falcon_detect()
1773 fext.hsync = h_syncs[mon_type] / fext.t; in falcon_detect()
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| /drivers/gpu/drm/stm/ |
| D | ltdc.c | 550 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; in ltdc_crtc_mode_set_nofb() local
572 hsync = vm.hsync_len - 1; in ltdc_crtc_mode_set_nofb()
574 accum_hbp = hsync + vm.hback_porch; in ltdc_crtc_mode_set_nofb()
600 val = (hsync << 16) | vsync; in ltdc_crtc_mode_set_nofb()
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