1 /*
2 * Synopsys DDR ECC Driver
3 * This driver is based on ppc4xx_edac.c drivers
4 *
5 * Copyright (C) 2012 - 2014 Xilinx, Inc.
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details
20 */
21
22 #include <linux/edac.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28
29 #include "edac_module.h"
30
31 /* Number of cs_rows needed per memory controller */
32 #define SYNPS_EDAC_NR_CSROWS 1
33
34 /* Number of channels per memory controller */
35 #define SYNPS_EDAC_NR_CHANS 1
36
37 /* Granularity of reported error in bytes */
38 #define SYNPS_EDAC_ERR_GRAIN 1
39
40 #define SYNPS_EDAC_MSG_SIZE 256
41
42 #define SYNPS_EDAC_MOD_STRING "synps_edac"
43 #define SYNPS_EDAC_MOD_VER "1"
44
45 /* Synopsys DDR memory controller registers that are relevant to ECC */
46 #define CTRL_OFST 0x0
47 #define T_ZQ_OFST 0xA4
48
49 /* ECC control register */
50 #define ECC_CTRL_OFST 0xC4
51 /* ECC log register */
52 #define CE_LOG_OFST 0xC8
53 /* ECC address register */
54 #define CE_ADDR_OFST 0xCC
55 /* ECC data[31:0] register */
56 #define CE_DATA_31_0_OFST 0xD0
57
58 /* Uncorrectable error info registers */
59 #define UE_LOG_OFST 0xDC
60 #define UE_ADDR_OFST 0xE0
61 #define UE_DATA_31_0_OFST 0xE4
62
63 #define STAT_OFST 0xF0
64 #define SCRUB_OFST 0xF4
65
66 /* Control register bit field definitions */
67 #define CTRL_BW_MASK 0xC
68 #define CTRL_BW_SHIFT 2
69
70 #define DDRCTL_WDTH_16 1
71 #define DDRCTL_WDTH_32 0
72
73 /* ZQ register bit field definitions */
74 #define T_ZQ_DDRMODE_MASK 0x2
75
76 /* ECC control register bit field definitions */
77 #define ECC_CTRL_CLR_CE_ERR 0x2
78 #define ECC_CTRL_CLR_UE_ERR 0x1
79
80 /* ECC correctable/uncorrectable error log register definitions */
81 #define LOG_VALID 0x1
82 #define CE_LOG_BITPOS_MASK 0xFE
83 #define CE_LOG_BITPOS_SHIFT 1
84
85 /* ECC correctable/uncorrectable error address register definitions */
86 #define ADDR_COL_MASK 0xFFF
87 #define ADDR_ROW_MASK 0xFFFF000
88 #define ADDR_ROW_SHIFT 12
89 #define ADDR_BANK_MASK 0x70000000
90 #define ADDR_BANK_SHIFT 28
91
92 /* ECC statistic register definitions */
93 #define STAT_UECNT_MASK 0xFF
94 #define STAT_CECNT_MASK 0xFF00
95 #define STAT_CECNT_SHIFT 8
96
97 /* ECC scrub register definitions */
98 #define SCRUB_MODE_MASK 0x7
99 #define SCRUB_MODE_SECDED 0x4
100
101 /* DDR ECC Quirks */
102 #define DDR_ECC_INTR_SUPPORT BIT(0)
103 #define DDR_ECC_DATA_POISON_SUPPORT BIT(1)
104
105 /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
106 /* ECC Configuration Registers */
107 #define ECC_CFG0_OFST 0x70
108 #define ECC_CFG1_OFST 0x74
109
110 /* ECC Status Register */
111 #define ECC_STAT_OFST 0x78
112
113 /* ECC Clear Register */
114 #define ECC_CLR_OFST 0x7C
115
116 /* ECC Error count Register */
117 #define ECC_ERRCNT_OFST 0x80
118
119 /* ECC Corrected Error Address Register */
120 #define ECC_CEADDR0_OFST 0x84
121 #define ECC_CEADDR1_OFST 0x88
122
123 /* ECC Syndrome Registers */
124 #define ECC_CSYND0_OFST 0x8C
125 #define ECC_CSYND1_OFST 0x90
126 #define ECC_CSYND2_OFST 0x94
127
128 /* ECC Bit Mask0 Address Register */
129 #define ECC_BITMASK0_OFST 0x98
130 #define ECC_BITMASK1_OFST 0x9C
131 #define ECC_BITMASK2_OFST 0xA0
132
133 /* ECC UnCorrected Error Address Register */
134 #define ECC_UEADDR0_OFST 0xA4
135 #define ECC_UEADDR1_OFST 0xA8
136
137 /* ECC Syndrome Registers */
138 #define ECC_UESYND0_OFST 0xAC
139 #define ECC_UESYND1_OFST 0xB0
140 #define ECC_UESYND2_OFST 0xB4
141
142 /* ECC Poison Address Reg */
143 #define ECC_POISON0_OFST 0xB8
144 #define ECC_POISON1_OFST 0xBC
145
146 #define ECC_ADDRMAP0_OFFSET 0x200
147
148 /* Control register bitfield definitions */
149 #define ECC_CTRL_BUSWIDTH_MASK 0x3000
150 #define ECC_CTRL_BUSWIDTH_SHIFT 12
151 #define ECC_CTRL_CLR_CE_ERRCNT BIT(2)
152 #define ECC_CTRL_CLR_UE_ERRCNT BIT(3)
153
154 /* DDR Control Register width definitions */
155 #define DDRCTL_EWDTH_16 2
156 #define DDRCTL_EWDTH_32 1
157 #define DDRCTL_EWDTH_64 0
158
159 /* ECC status register definitions */
160 #define ECC_STAT_UECNT_MASK 0xF0000
161 #define ECC_STAT_UECNT_SHIFT 16
162 #define ECC_STAT_CECNT_MASK 0xF00
163 #define ECC_STAT_CECNT_SHIFT 8
164 #define ECC_STAT_BITNUM_MASK 0x7F
165
166 /* DDR QOS Interrupt register definitions */
167 #define DDR_QOS_IRQ_STAT_OFST 0x20200
168 #define DDR_QOSUE_MASK 0x4
169 #define DDR_QOSCE_MASK 0x2
170 #define ECC_CE_UE_INTR_MASK 0x6
171 #define DDR_QOS_IRQ_EN_OFST 0x20208
172 #define DDR_QOS_IRQ_DB_OFST 0x2020C
173
174 /* ECC Corrected Error Register Mask and Shifts*/
175 #define ECC_CEADDR0_RW_MASK 0x3FFFF
176 #define ECC_CEADDR0_RNK_MASK BIT(24)
177 #define ECC_CEADDR1_BNKGRP_MASK 0x3000000
178 #define ECC_CEADDR1_BNKNR_MASK 0x70000
179 #define ECC_CEADDR1_BLKNR_MASK 0xFFF
180 #define ECC_CEADDR1_BNKGRP_SHIFT 24
181 #define ECC_CEADDR1_BNKNR_SHIFT 16
182
183 /* ECC Poison register shifts */
184 #define ECC_POISON0_RANK_SHIFT 24
185 #define ECC_POISON0_RANK_MASK BIT(24)
186 #define ECC_POISON0_COLUMN_SHIFT 0
187 #define ECC_POISON0_COLUMN_MASK 0xFFF
188 #define ECC_POISON1_BG_SHIFT 28
189 #define ECC_POISON1_BG_MASK 0x30000000
190 #define ECC_POISON1_BANKNR_SHIFT 24
191 #define ECC_POISON1_BANKNR_MASK 0x7000000
192 #define ECC_POISON1_ROW_SHIFT 0
193 #define ECC_POISON1_ROW_MASK 0x3FFFF
194
195 /* DDR Memory type defines */
196 #define MEM_TYPE_DDR3 0x1
197 #define MEM_TYPE_LPDDR3 0x8
198 #define MEM_TYPE_DDR2 0x4
199 #define MEM_TYPE_DDR4 0x10
200 #define MEM_TYPE_LPDDR4 0x20
201
202 /* DDRC Software control register */
203 #define DDRC_SWCTL 0x320
204
205 /* DDRC ECC CE & UE poison mask */
206 #define ECC_CEPOISON_MASK 0x3
207 #define ECC_UEPOISON_MASK 0x1
208
209 /* DDRC Device config masks */
210 #define DDRC_MSTR_CFG_MASK 0xC0000000
211 #define DDRC_MSTR_CFG_SHIFT 30
212 #define DDRC_MSTR_CFG_X4_MASK 0x0
213 #define DDRC_MSTR_CFG_X8_MASK 0x1
214 #define DDRC_MSTR_CFG_X16_MASK 0x2
215 #define DDRC_MSTR_CFG_X32_MASK 0x3
216
217 #define DDR_MAX_ROW_SHIFT 18
218 #define DDR_MAX_COL_SHIFT 14
219 #define DDR_MAX_BANK_SHIFT 3
220 #define DDR_MAX_BANKGRP_SHIFT 2
221
222 #define ROW_MAX_VAL_MASK 0xF
223 #define COL_MAX_VAL_MASK 0xF
224 #define BANK_MAX_VAL_MASK 0x1F
225 #define BANKGRP_MAX_VAL_MASK 0x1F
226 #define RANK_MAX_VAL_MASK 0x1F
227
228 #define ROW_B0_BASE 6
229 #define ROW_B1_BASE 7
230 #define ROW_B2_BASE 8
231 #define ROW_B3_BASE 9
232 #define ROW_B4_BASE 10
233 #define ROW_B5_BASE 11
234 #define ROW_B6_BASE 12
235 #define ROW_B7_BASE 13
236 #define ROW_B8_BASE 14
237 #define ROW_B9_BASE 15
238 #define ROW_B10_BASE 16
239 #define ROW_B11_BASE 17
240 #define ROW_B12_BASE 18
241 #define ROW_B13_BASE 19
242 #define ROW_B14_BASE 20
243 #define ROW_B15_BASE 21
244 #define ROW_B16_BASE 22
245 #define ROW_B17_BASE 23
246
247 #define COL_B2_BASE 2
248 #define COL_B3_BASE 3
249 #define COL_B4_BASE 4
250 #define COL_B5_BASE 5
251 #define COL_B6_BASE 6
252 #define COL_B7_BASE 7
253 #define COL_B8_BASE 8
254 #define COL_B9_BASE 9
255 #define COL_B10_BASE 10
256 #define COL_B11_BASE 11
257 #define COL_B12_BASE 12
258 #define COL_B13_BASE 13
259
260 #define BANK_B0_BASE 2
261 #define BANK_B1_BASE 3
262 #define BANK_B2_BASE 4
263
264 #define BANKGRP_B0_BASE 2
265 #define BANKGRP_B1_BASE 3
266
267 #define RANK_B0_BASE 6
268
269 /**
270 * struct ecc_error_info - ECC error log information.
271 * @row: Row number.
272 * @col: Column number.
273 * @bank: Bank number.
274 * @bitpos: Bit position.
275 * @data: Data causing the error.
276 * @bankgrpnr: Bank group number.
277 * @blknr: Block number.
278 */
279 struct ecc_error_info {
280 u32 row;
281 u32 col;
282 u32 bank;
283 u32 bitpos;
284 u32 data;
285 u32 bankgrpnr;
286 u32 blknr;
287 };
288
289 /**
290 * struct synps_ecc_status - ECC status information to report.
291 * @ce_cnt: Correctable error count.
292 * @ue_cnt: Uncorrectable error count.
293 * @ceinfo: Correctable error log information.
294 * @ueinfo: Uncorrectable error log information.
295 */
296 struct synps_ecc_status {
297 u32 ce_cnt;
298 u32 ue_cnt;
299 struct ecc_error_info ceinfo;
300 struct ecc_error_info ueinfo;
301 };
302
303 /**
304 * struct synps_edac_priv - DDR memory controller private instance data.
305 * @baseaddr: Base address of the DDR controller.
306 * @message: Buffer for framing the event specific info.
307 * @stat: ECC status information.
308 * @p_data: Platform data.
309 * @ce_cnt: Correctable Error count.
310 * @ue_cnt: Uncorrectable Error count.
311 * @poison_addr: Data poison address.
312 * @row_shift: Bit shifts for row bit.
313 * @col_shift: Bit shifts for column bit.
314 * @bank_shift: Bit shifts for bank bit.
315 * @bankgrp_shift: Bit shifts for bank group bit.
316 * @rank_shift: Bit shifts for rank bit.
317 */
318 struct synps_edac_priv {
319 void __iomem *baseaddr;
320 char message[SYNPS_EDAC_MSG_SIZE];
321 struct synps_ecc_status stat;
322 const struct synps_platform_data *p_data;
323 u32 ce_cnt;
324 u32 ue_cnt;
325 #ifdef CONFIG_EDAC_DEBUG
326 ulong poison_addr;
327 u32 row_shift[18];
328 u32 col_shift[14];
329 u32 bank_shift[3];
330 u32 bankgrp_shift[2];
331 u32 rank_shift[1];
332 #endif
333 };
334
335 /**
336 * struct synps_platform_data - synps platform data structure.
337 * @get_error_info: Get EDAC error info.
338 * @get_mtype: Get mtype.
339 * @get_dtype: Get dtype.
340 * @get_ecc_state: Get ECC state.
341 * @quirks: To differentiate IPs.
342 */
343 struct synps_platform_data {
344 int (*get_error_info)(struct synps_edac_priv *priv);
345 enum mem_type (*get_mtype)(const void __iomem *base);
346 enum dev_type (*get_dtype)(const void __iomem *base);
347 bool (*get_ecc_state)(void __iomem *base);
348 int quirks;
349 };
350
351 /**
352 * zynq_get_error_info - Get the current ECC error info.
353 * @priv: DDR memory controller private instance data.
354 *
355 * Return: one if there is no error, otherwise zero.
356 */
zynq_get_error_info(struct synps_edac_priv * priv)357 static int zynq_get_error_info(struct synps_edac_priv *priv)
358 {
359 struct synps_ecc_status *p;
360 u32 regval, clearval = 0;
361 void __iomem *base;
362
363 base = priv->baseaddr;
364 p = &priv->stat;
365
366 regval = readl(base + STAT_OFST);
367 if (!regval)
368 return 1;
369
370 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT;
371 p->ue_cnt = regval & STAT_UECNT_MASK;
372
373 regval = readl(base + CE_LOG_OFST);
374 if (!(p->ce_cnt && (regval & LOG_VALID)))
375 goto ue_err;
376
377 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT;
378 regval = readl(base + CE_ADDR_OFST);
379 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
380 p->ceinfo.col = regval & ADDR_COL_MASK;
381 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
382 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST);
383 edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos,
384 p->ceinfo.data);
385 clearval = ECC_CTRL_CLR_CE_ERR;
386
387 ue_err:
388 regval = readl(base + UE_LOG_OFST);
389 if (!(p->ue_cnt && (regval & LOG_VALID)))
390 goto out;
391
392 regval = readl(base + UE_ADDR_OFST);
393 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
394 p->ueinfo.col = regval & ADDR_COL_MASK;
395 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
396 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST);
397 clearval |= ECC_CTRL_CLR_UE_ERR;
398
399 out:
400 writel(clearval, base + ECC_CTRL_OFST);
401 writel(0x0, base + ECC_CTRL_OFST);
402
403 return 0;
404 }
405
406 /**
407 * zynqmp_get_error_info - Get the current ECC error info.
408 * @priv: DDR memory controller private instance data.
409 *
410 * Return: one if there is no error otherwise returns zero.
411 */
zynqmp_get_error_info(struct synps_edac_priv * priv)412 static int zynqmp_get_error_info(struct synps_edac_priv *priv)
413 {
414 struct synps_ecc_status *p;
415 u32 regval, clearval = 0;
416 void __iomem *base;
417
418 base = priv->baseaddr;
419 p = &priv->stat;
420
421 regval = readl(base + ECC_STAT_OFST);
422 if (!regval)
423 return 1;
424
425 p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT;
426 p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT;
427 if (!p->ce_cnt)
428 goto ue_err;
429
430 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
431
432 regval = readl(base + ECC_CEADDR0_OFST);
433 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK);
434 regval = readl(base + ECC_CEADDR1_OFST);
435 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
436 ECC_CEADDR1_BNKNR_SHIFT;
437 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
438 ECC_CEADDR1_BNKGRP_SHIFT;
439 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
440 p->ceinfo.data = readl(base + ECC_CSYND0_OFST);
441 edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n",
442 readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST),
443 readl(base + ECC_CSYND2_OFST));
444 ue_err:
445 if (!p->ue_cnt)
446 goto out;
447
448 regval = readl(base + ECC_UEADDR0_OFST);
449 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK);
450 regval = readl(base + ECC_UEADDR1_OFST);
451 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
452 ECC_CEADDR1_BNKGRP_SHIFT;
453 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
454 ECC_CEADDR1_BNKNR_SHIFT;
455 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
456 p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
457 out:
458 clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT;
459 clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT;
460 writel(clearval, base + ECC_CLR_OFST);
461 writel(0x0, base + ECC_CLR_OFST);
462
463 return 0;
464 }
465
466 /**
467 * handle_error - Handle Correctable and Uncorrectable errors.
468 * @mci: EDAC memory controller instance.
469 * @p: Synopsys ECC status structure.
470 *
471 * Handles ECC correctable and uncorrectable errors.
472 */
handle_error(struct mem_ctl_info * mci,struct synps_ecc_status * p)473 static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
474 {
475 struct synps_edac_priv *priv = mci->pvt_info;
476 struct ecc_error_info *pinf;
477
478 if (p->ce_cnt) {
479 pinf = &p->ceinfo;
480 if (!priv->p_data->quirks) {
481 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
482 "DDR ECC error type:%s Row %d Bank %d Col %d ",
483 "CE", pinf->row, pinf->bank, pinf->col);
484 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
485 "Bit Position: %d Data: 0x%08x\n",
486 pinf->bitpos, pinf->data);
487 } else {
488 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
489 "DDR ECC error type:%s Row %d Bank %d Col %d ",
490 "CE", pinf->row, pinf->bank, pinf->col);
491 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
492 "BankGroup Number %d Block Number %d ",
493 pinf->bankgrpnr, pinf->blknr);
494 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
495 "Bit Position: %d Data: 0x%08x\n",
496 pinf->bitpos, pinf->data);
497 }
498
499 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
500 p->ce_cnt, 0, 0, 0, 0, 0, -1,
501 priv->message, "");
502 }
503
504 if (p->ue_cnt) {
505 pinf = &p->ueinfo;
506 if (!priv->p_data->quirks) {
507 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
508 "DDR ECC error type :%s Row %d Bank %d Col %d ",
509 "UE", pinf->row, pinf->bank, pinf->col);
510 } else {
511 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
512 "DDR ECC error type :%s Row %d Bank %d Col %d ",
513 "UE", pinf->row, pinf->bank, pinf->col);
514 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
515 "BankGroup Number %d Block Number %d",
516 pinf->bankgrpnr, pinf->blknr);
517 }
518
519 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
520 p->ue_cnt, 0, 0, 0, 0, 0, -1,
521 priv->message, "");
522 }
523
524 memset(p, 0, sizeof(*p));
525 }
526
527 /**
528 * intr_handler - Interrupt Handler for ECC interrupts.
529 * @irq: IRQ number.
530 * @dev_id: Device ID.
531 *
532 * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise.
533 */
intr_handler(int irq,void * dev_id)534 static irqreturn_t intr_handler(int irq, void *dev_id)
535 {
536 const struct synps_platform_data *p_data;
537 struct mem_ctl_info *mci = dev_id;
538 struct synps_edac_priv *priv;
539 int status, regval;
540
541 priv = mci->pvt_info;
542 p_data = priv->p_data;
543
544 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
545 regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK);
546 if (!(regval & ECC_CE_UE_INTR_MASK))
547 return IRQ_NONE;
548
549 status = p_data->get_error_info(priv);
550 if (status)
551 return IRQ_NONE;
552
553 priv->ce_cnt += priv->stat.ce_cnt;
554 priv->ue_cnt += priv->stat.ue_cnt;
555 handle_error(mci, &priv->stat);
556
557 edac_dbg(3, "Total error count CE %d UE %d\n",
558 priv->ce_cnt, priv->ue_cnt);
559 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
560 return IRQ_HANDLED;
561 }
562
563 /**
564 * check_errors - Check controller for ECC errors.
565 * @mci: EDAC memory controller instance.
566 *
567 * Check and post ECC errors. Called by the polling thread.
568 */
check_errors(struct mem_ctl_info * mci)569 static void check_errors(struct mem_ctl_info *mci)
570 {
571 const struct synps_platform_data *p_data;
572 struct synps_edac_priv *priv;
573 int status;
574
575 priv = mci->pvt_info;
576 p_data = priv->p_data;
577
578 status = p_data->get_error_info(priv);
579 if (status)
580 return;
581
582 priv->ce_cnt += priv->stat.ce_cnt;
583 priv->ue_cnt += priv->stat.ue_cnt;
584 handle_error(mci, &priv->stat);
585
586 edac_dbg(3, "Total error count CE %d UE %d\n",
587 priv->ce_cnt, priv->ue_cnt);
588 }
589
590 /**
591 * zynq_get_dtype - Return the controller memory width.
592 * @base: DDR memory controller base address.
593 *
594 * Get the EDAC device type width appropriate for the current controller
595 * configuration.
596 *
597 * Return: a device type width enumeration.
598 */
zynq_get_dtype(const void __iomem * base)599 static enum dev_type zynq_get_dtype(const void __iomem *base)
600 {
601 enum dev_type dt;
602 u32 width;
603
604 width = readl(base + CTRL_OFST);
605 width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT;
606
607 switch (width) {
608 case DDRCTL_WDTH_16:
609 dt = DEV_X2;
610 break;
611 case DDRCTL_WDTH_32:
612 dt = DEV_X4;
613 break;
614 default:
615 dt = DEV_UNKNOWN;
616 }
617
618 return dt;
619 }
620
621 /**
622 * zynqmp_get_dtype - Return the controller memory width.
623 * @base: DDR memory controller base address.
624 *
625 * Get the EDAC device type width appropriate for the current controller
626 * configuration.
627 *
628 * Return: a device type width enumeration.
629 */
zynqmp_get_dtype(const void __iomem * base)630 static enum dev_type zynqmp_get_dtype(const void __iomem *base)
631 {
632 enum dev_type dt;
633 u32 width;
634
635 width = readl(base + CTRL_OFST);
636 width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
637 switch (width) {
638 case DDRCTL_EWDTH_16:
639 dt = DEV_X2;
640 break;
641 case DDRCTL_EWDTH_32:
642 dt = DEV_X4;
643 break;
644 case DDRCTL_EWDTH_64:
645 dt = DEV_X8;
646 break;
647 default:
648 dt = DEV_UNKNOWN;
649 }
650
651 return dt;
652 }
653
654 /**
655 * zynq_get_ecc_state - Return the controller ECC enable/disable status.
656 * @base: DDR memory controller base address.
657 *
658 * Get the ECC enable/disable status of the controller.
659 *
660 * Return: true if enabled, otherwise false.
661 */
zynq_get_ecc_state(void __iomem * base)662 static bool zynq_get_ecc_state(void __iomem *base)
663 {
664 enum dev_type dt;
665 u32 ecctype;
666
667 dt = zynq_get_dtype(base);
668 if (dt == DEV_UNKNOWN)
669 return false;
670
671 ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK;
672 if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2))
673 return true;
674
675 return false;
676 }
677
678 /**
679 * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
680 * @base: DDR memory controller base address.
681 *
682 * Get the ECC enable/disable status for the controller.
683 *
684 * Return: a ECC status boolean i.e true/false - enabled/disabled.
685 */
zynqmp_get_ecc_state(void __iomem * base)686 static bool zynqmp_get_ecc_state(void __iomem *base)
687 {
688 enum dev_type dt;
689 u32 ecctype;
690
691 dt = zynqmp_get_dtype(base);
692 if (dt == DEV_UNKNOWN)
693 return false;
694
695 ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK;
696 if ((ecctype == SCRUB_MODE_SECDED) &&
697 ((dt == DEV_X2) || (dt == DEV_X4) || (dt == DEV_X8)))
698 return true;
699
700 return false;
701 }
702
703 /**
704 * get_memsize - Read the size of the attached memory device.
705 *
706 * Return: the memory size in bytes.
707 */
get_memsize(void)708 static u32 get_memsize(void)
709 {
710 struct sysinfo inf;
711
712 si_meminfo(&inf);
713
714 return inf.totalram * inf.mem_unit;
715 }
716
717 /**
718 * zynq_get_mtype - Return the controller memory type.
719 * @base: Synopsys ECC status structure.
720 *
721 * Get the EDAC memory type appropriate for the current controller
722 * configuration.
723 *
724 * Return: a memory type enumeration.
725 */
zynq_get_mtype(const void __iomem * base)726 static enum mem_type zynq_get_mtype(const void __iomem *base)
727 {
728 enum mem_type mt;
729 u32 memtype;
730
731 memtype = readl(base + T_ZQ_OFST);
732
733 if (memtype & T_ZQ_DDRMODE_MASK)
734 mt = MEM_DDR3;
735 else
736 mt = MEM_DDR2;
737
738 return mt;
739 }
740
741 /**
742 * zynqmp_get_mtype - Returns controller memory type.
743 * @base: Synopsys ECC status structure.
744 *
745 * Get the EDAC memory type appropriate for the current controller
746 * configuration.
747 *
748 * Return: a memory type enumeration.
749 */
zynqmp_get_mtype(const void __iomem * base)750 static enum mem_type zynqmp_get_mtype(const void __iomem *base)
751 {
752 enum mem_type mt;
753 u32 memtype;
754
755 memtype = readl(base + CTRL_OFST);
756
757 if ((memtype & MEM_TYPE_DDR3) || (memtype & MEM_TYPE_LPDDR3))
758 mt = MEM_DDR3;
759 else if (memtype & MEM_TYPE_DDR2)
760 mt = MEM_RDDR2;
761 else if ((memtype & MEM_TYPE_LPDDR4) || (memtype & MEM_TYPE_DDR4))
762 mt = MEM_DDR4;
763 else
764 mt = MEM_EMPTY;
765
766 return mt;
767 }
768
769 /**
770 * init_csrows - Initialize the csrow data.
771 * @mci: EDAC memory controller instance.
772 *
773 * Initialize the chip select rows associated with the EDAC memory
774 * controller instance.
775 */
init_csrows(struct mem_ctl_info * mci)776 static void init_csrows(struct mem_ctl_info *mci)
777 {
778 struct synps_edac_priv *priv = mci->pvt_info;
779 const struct synps_platform_data *p_data;
780 struct csrow_info *csi;
781 struct dimm_info *dimm;
782 u32 size, row;
783 int j;
784
785 p_data = priv->p_data;
786
787 for (row = 0; row < mci->nr_csrows; row++) {
788 csi = mci->csrows[row];
789 size = get_memsize();
790
791 for (j = 0; j < csi->nr_channels; j++) {
792 dimm = csi->channels[j]->dimm;
793 dimm->edac_mode = EDAC_FLAG_SECDED;
794 dimm->mtype = p_data->get_mtype(priv->baseaddr);
795 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
796 dimm->grain = SYNPS_EDAC_ERR_GRAIN;
797 dimm->dtype = p_data->get_dtype(priv->baseaddr);
798 }
799 }
800 }
801
802 /**
803 * mc_init - Initialize one driver instance.
804 * @mci: EDAC memory controller instance.
805 * @pdev: platform device.
806 *
807 * Perform initialization of the EDAC memory controller instance and
808 * related driver-private data associated with the memory controller the
809 * instance is bound to.
810 */
mc_init(struct mem_ctl_info * mci,struct platform_device * pdev)811 static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
812 {
813 struct synps_edac_priv *priv;
814
815 mci->pdev = &pdev->dev;
816 priv = mci->pvt_info;
817 platform_set_drvdata(pdev, mci);
818
819 /* Initialize controller capabilities and configuration */
820 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2;
821 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
822 mci->scrub_cap = SCRUB_HW_SRC;
823 mci->scrub_mode = SCRUB_NONE;
824
825 mci->edac_cap = EDAC_FLAG_SECDED;
826 mci->ctl_name = "synps_ddr_controller";
827 mci->dev_name = SYNPS_EDAC_MOD_STRING;
828 mci->mod_name = SYNPS_EDAC_MOD_VER;
829
830 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
831 edac_op_state = EDAC_OPSTATE_INT;
832 } else {
833 edac_op_state = EDAC_OPSTATE_POLL;
834 mci->edac_check = check_errors;
835 }
836
837 mci->ctl_page_to_phys = NULL;
838
839 init_csrows(mci);
840 }
841
enable_intr(struct synps_edac_priv * priv)842 static void enable_intr(struct synps_edac_priv *priv)
843 {
844 /* Enable UE/CE Interrupts */
845 writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
846 priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
847 }
848
disable_intr(struct synps_edac_priv * priv)849 static void disable_intr(struct synps_edac_priv *priv)
850 {
851 /* Disable UE/CE Interrupts */
852 writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
853 priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
854 }
855
setup_irq(struct mem_ctl_info * mci,struct platform_device * pdev)856 static int setup_irq(struct mem_ctl_info *mci,
857 struct platform_device *pdev)
858 {
859 struct synps_edac_priv *priv = mci->pvt_info;
860 int ret, irq;
861
862 irq = platform_get_irq(pdev, 0);
863 if (irq < 0) {
864 edac_printk(KERN_ERR, EDAC_MC,
865 "No IRQ %d in DT\n", irq);
866 return irq;
867 }
868
869 ret = devm_request_irq(&pdev->dev, irq, intr_handler,
870 0, dev_name(&pdev->dev), mci);
871 if (ret < 0) {
872 edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n");
873 return ret;
874 }
875
876 enable_intr(priv);
877
878 return 0;
879 }
880
881 static const struct synps_platform_data zynq_edac_def = {
882 .get_error_info = zynq_get_error_info,
883 .get_mtype = zynq_get_mtype,
884 .get_dtype = zynq_get_dtype,
885 .get_ecc_state = zynq_get_ecc_state,
886 .quirks = 0,
887 };
888
889 static const struct synps_platform_data zynqmp_edac_def = {
890 .get_error_info = zynqmp_get_error_info,
891 .get_mtype = zynqmp_get_mtype,
892 .get_dtype = zynqmp_get_dtype,
893 .get_ecc_state = zynqmp_get_ecc_state,
894 .quirks = (DDR_ECC_INTR_SUPPORT
895 #ifdef CONFIG_EDAC_DEBUG
896 | DDR_ECC_DATA_POISON_SUPPORT
897 #endif
898 ),
899 };
900
901 static const struct of_device_id synps_edac_match[] = {
902 {
903 .compatible = "xlnx,zynq-ddrc-a05",
904 .data = (void *)&zynq_edac_def
905 },
906 {
907 .compatible = "xlnx,zynqmp-ddrc-2.40a",
908 .data = (void *)&zynqmp_edac_def
909 },
910 {
911 /* end of table */
912 }
913 };
914
915 MODULE_DEVICE_TABLE(of, synps_edac_match);
916
917 #ifdef CONFIG_EDAC_DEBUG
918 #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
919
920 /**
921 * ddr_poison_setup - Update poison registers.
922 * @priv: DDR memory controller private instance data.
923 *
924 * Update poison registers as per DDR mapping.
925 * Return: none.
926 */
ddr_poison_setup(struct synps_edac_priv * priv)927 static void ddr_poison_setup(struct synps_edac_priv *priv)
928 {
929 int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval;
930 int index;
931 ulong hif_addr = 0;
932
933 hif_addr = priv->poison_addr >> 3;
934
935 for (index = 0; index < DDR_MAX_ROW_SHIFT; index++) {
936 if (priv->row_shift[index])
937 row |= (((hif_addr >> priv->row_shift[index]) &
938 BIT(0)) << index);
939 else
940 break;
941 }
942
943 for (index = 0; index < DDR_MAX_COL_SHIFT; index++) {
944 if (priv->col_shift[index] || index < 3)
945 col |= (((hif_addr >> priv->col_shift[index]) &
946 BIT(0)) << index);
947 else
948 break;
949 }
950
951 for (index = 0; index < DDR_MAX_BANK_SHIFT; index++) {
952 if (priv->bank_shift[index])
953 bank |= (((hif_addr >> priv->bank_shift[index]) &
954 BIT(0)) << index);
955 else
956 break;
957 }
958
959 for (index = 0; index < DDR_MAX_BANKGRP_SHIFT; index++) {
960 if (priv->bankgrp_shift[index])
961 bankgrp |= (((hif_addr >> priv->bankgrp_shift[index])
962 & BIT(0)) << index);
963 else
964 break;
965 }
966
967 if (priv->rank_shift[0])
968 rank = (hif_addr >> priv->rank_shift[0]) & BIT(0);
969
970 regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK;
971 regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK;
972 writel(regval, priv->baseaddr + ECC_POISON0_OFST);
973
974 regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK;
975 regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK;
976 regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK;
977 writel(regval, priv->baseaddr + ECC_POISON1_OFST);
978 }
979
inject_data_error_show(struct device * dev,struct device_attribute * mattr,char * data)980 static ssize_t inject_data_error_show(struct device *dev,
981 struct device_attribute *mattr,
982 char *data)
983 {
984 struct mem_ctl_info *mci = to_mci(dev);
985 struct synps_edac_priv *priv = mci->pvt_info;
986
987 return sprintf(data, "Poison0 Addr: 0x%08x\n\rPoison1 Addr: 0x%08x\n\r"
988 "Error injection Address: 0x%lx\n\r",
989 readl(priv->baseaddr + ECC_POISON0_OFST),
990 readl(priv->baseaddr + ECC_POISON1_OFST),
991 priv->poison_addr);
992 }
993
inject_data_error_store(struct device * dev,struct device_attribute * mattr,const char * data,size_t count)994 static ssize_t inject_data_error_store(struct device *dev,
995 struct device_attribute *mattr,
996 const char *data, size_t count)
997 {
998 struct mem_ctl_info *mci = to_mci(dev);
999 struct synps_edac_priv *priv = mci->pvt_info;
1000
1001 if (kstrtoul(data, 0, &priv->poison_addr))
1002 return -EINVAL;
1003
1004 ddr_poison_setup(priv);
1005
1006 return count;
1007 }
1008
inject_data_poison_show(struct device * dev,struct device_attribute * mattr,char * data)1009 static ssize_t inject_data_poison_show(struct device *dev,
1010 struct device_attribute *mattr,
1011 char *data)
1012 {
1013 struct mem_ctl_info *mci = to_mci(dev);
1014 struct synps_edac_priv *priv = mci->pvt_info;
1015
1016 return sprintf(data, "Data Poisoning: %s\n\r",
1017 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3)
1018 ? ("Correctable Error") : ("UnCorrectable Error"));
1019 }
1020
inject_data_poison_store(struct device * dev,struct device_attribute * mattr,const char * data,size_t count)1021 static ssize_t inject_data_poison_store(struct device *dev,
1022 struct device_attribute *mattr,
1023 const char *data, size_t count)
1024 {
1025 struct mem_ctl_info *mci = to_mci(dev);
1026 struct synps_edac_priv *priv = mci->pvt_info;
1027
1028 writel(0, priv->baseaddr + DDRC_SWCTL);
1029 if (strncmp(data, "CE", 2) == 0)
1030 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1031 else
1032 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
1033 writel(1, priv->baseaddr + DDRC_SWCTL);
1034
1035 return count;
1036 }
1037
1038 static DEVICE_ATTR_RW(inject_data_error);
1039 static DEVICE_ATTR_RW(inject_data_poison);
1040
edac_create_sysfs_attributes(struct mem_ctl_info * mci)1041 static int edac_create_sysfs_attributes(struct mem_ctl_info *mci)
1042 {
1043 int rc;
1044
1045 rc = device_create_file(&mci->dev, &dev_attr_inject_data_error);
1046 if (rc < 0)
1047 return rc;
1048 rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison);
1049 if (rc < 0)
1050 return rc;
1051 return 0;
1052 }
1053
edac_remove_sysfs_attributes(struct mem_ctl_info * mci)1054 static void edac_remove_sysfs_attributes(struct mem_ctl_info *mci)
1055 {
1056 device_remove_file(&mci->dev, &dev_attr_inject_data_error);
1057 device_remove_file(&mci->dev, &dev_attr_inject_data_poison);
1058 }
1059
setup_row_address_map(struct synps_edac_priv * priv,u32 * addrmap)1060 static void setup_row_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1061 {
1062 u32 addrmap_row_b2_10;
1063 int index;
1064
1065 priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE;
1066 priv->row_shift[1] = ((addrmap[5] >> 8) &
1067 ROW_MAX_VAL_MASK) + ROW_B1_BASE;
1068
1069 addrmap_row_b2_10 = (addrmap[5] >> 16) & ROW_MAX_VAL_MASK;
1070 if (addrmap_row_b2_10 != ROW_MAX_VAL_MASK) {
1071 for (index = 2; index < 11; index++)
1072 priv->row_shift[index] = addrmap_row_b2_10 +
1073 index + ROW_B0_BASE;
1074
1075 } else {
1076 priv->row_shift[2] = (addrmap[9] &
1077 ROW_MAX_VAL_MASK) + ROW_B2_BASE;
1078 priv->row_shift[3] = ((addrmap[9] >> 8) &
1079 ROW_MAX_VAL_MASK) + ROW_B3_BASE;
1080 priv->row_shift[4] = ((addrmap[9] >> 16) &
1081 ROW_MAX_VAL_MASK) + ROW_B4_BASE;
1082 priv->row_shift[5] = ((addrmap[9] >> 24) &
1083 ROW_MAX_VAL_MASK) + ROW_B5_BASE;
1084 priv->row_shift[6] = (addrmap[10] &
1085 ROW_MAX_VAL_MASK) + ROW_B6_BASE;
1086 priv->row_shift[7] = ((addrmap[10] >> 8) &
1087 ROW_MAX_VAL_MASK) + ROW_B7_BASE;
1088 priv->row_shift[8] = ((addrmap[10] >> 16) &
1089 ROW_MAX_VAL_MASK) + ROW_B8_BASE;
1090 priv->row_shift[9] = ((addrmap[10] >> 24) &
1091 ROW_MAX_VAL_MASK) + ROW_B9_BASE;
1092 priv->row_shift[10] = (addrmap[11] &
1093 ROW_MAX_VAL_MASK) + ROW_B10_BASE;
1094 }
1095
1096 priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) ==
1097 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[5] >> 24) &
1098 ROW_MAX_VAL_MASK) + ROW_B11_BASE);
1099 priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) ==
1100 ROW_MAX_VAL_MASK) ? 0 : ((addrmap[6] &
1101 ROW_MAX_VAL_MASK) + ROW_B12_BASE);
1102 priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) ==
1103 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 8) &
1104 ROW_MAX_VAL_MASK) + ROW_B13_BASE);
1105 priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) ==
1106 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 16) &
1107 ROW_MAX_VAL_MASK) + ROW_B14_BASE);
1108 priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) ==
1109 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 24) &
1110 ROW_MAX_VAL_MASK) + ROW_B15_BASE);
1111 priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) ==
1112 ROW_MAX_VAL_MASK) ? 0 : ((addrmap[7] &
1113 ROW_MAX_VAL_MASK) + ROW_B16_BASE);
1114 priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) ==
1115 ROW_MAX_VAL_MASK) ? 0 : (((addrmap[7] >> 8) &
1116 ROW_MAX_VAL_MASK) + ROW_B17_BASE);
1117 }
1118
setup_column_address_map(struct synps_edac_priv * priv,u32 * addrmap)1119 static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1120 {
1121 u32 width, memtype;
1122 int index;
1123
1124 memtype = readl(priv->baseaddr + CTRL_OFST);
1125 width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
1126
1127 priv->col_shift[0] = 0;
1128 priv->col_shift[1] = 1;
1129 priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE;
1130 priv->col_shift[3] = ((addrmap[2] >> 8) &
1131 COL_MAX_VAL_MASK) + COL_B3_BASE;
1132 priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) ==
1133 COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 16) &
1134 COL_MAX_VAL_MASK) + COL_B4_BASE);
1135 priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) ==
1136 COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 24) &
1137 COL_MAX_VAL_MASK) + COL_B5_BASE);
1138 priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) ==
1139 COL_MAX_VAL_MASK) ? 0 : ((addrmap[3] &
1140 COL_MAX_VAL_MASK) + COL_B6_BASE);
1141 priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) ==
1142 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 8) &
1143 COL_MAX_VAL_MASK) + COL_B7_BASE);
1144 priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) ==
1145 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 16) &
1146 COL_MAX_VAL_MASK) + COL_B8_BASE);
1147 priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) ==
1148 COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 24) &
1149 COL_MAX_VAL_MASK) + COL_B9_BASE);
1150 if (width == DDRCTL_EWDTH_64) {
1151 if (memtype & MEM_TYPE_LPDDR3) {
1152 priv->col_shift[10] = ((addrmap[4] &
1153 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1154 ((addrmap[4] & COL_MAX_VAL_MASK) +
1155 COL_B10_BASE);
1156 priv->col_shift[11] = (((addrmap[4] >> 8) &
1157 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1158 (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
1159 COL_B11_BASE);
1160 } else {
1161 priv->col_shift[11] = ((addrmap[4] &
1162 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1163 ((addrmap[4] & COL_MAX_VAL_MASK) +
1164 COL_B10_BASE);
1165 priv->col_shift[13] = (((addrmap[4] >> 8) &
1166 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1167 (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
1168 COL_B11_BASE);
1169 }
1170 } else if (width == DDRCTL_EWDTH_32) {
1171 if (memtype & MEM_TYPE_LPDDR3) {
1172 priv->col_shift[10] = (((addrmap[3] >> 24) &
1173 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1174 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1175 COL_B9_BASE);
1176 priv->col_shift[11] = ((addrmap[4] &
1177 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1178 ((addrmap[4] & COL_MAX_VAL_MASK) +
1179 COL_B10_BASE);
1180 } else {
1181 priv->col_shift[11] = (((addrmap[3] >> 24) &
1182 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1183 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1184 COL_B9_BASE);
1185 priv->col_shift[13] = ((addrmap[4] &
1186 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1187 ((addrmap[4] & COL_MAX_VAL_MASK) +
1188 COL_B10_BASE);
1189 }
1190 } else {
1191 if (memtype & MEM_TYPE_LPDDR3) {
1192 priv->col_shift[10] = (((addrmap[3] >> 16) &
1193 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1194 (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
1195 COL_B8_BASE);
1196 priv->col_shift[11] = (((addrmap[3] >> 24) &
1197 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1198 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1199 COL_B9_BASE);
1200 priv->col_shift[13] = ((addrmap[4] &
1201 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1202 ((addrmap[4] & COL_MAX_VAL_MASK) +
1203 COL_B10_BASE);
1204 } else {
1205 priv->col_shift[11] = (((addrmap[3] >> 16) &
1206 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1207 (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
1208 COL_B8_BASE);
1209 priv->col_shift[13] = (((addrmap[3] >> 24) &
1210 COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
1211 (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
1212 COL_B9_BASE);
1213 }
1214 }
1215
1216 if (width) {
1217 for (index = 9; index > width; index--) {
1218 priv->col_shift[index] = priv->col_shift[index - width];
1219 priv->col_shift[index - width] = 0;
1220 }
1221 }
1222
1223 }
1224
setup_bank_address_map(struct synps_edac_priv * priv,u32 * addrmap)1225 static void setup_bank_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1226 {
1227 priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE;
1228 priv->bank_shift[1] = ((addrmap[1] >> 8) &
1229 BANK_MAX_VAL_MASK) + BANK_B1_BASE;
1230 priv->bank_shift[2] = (((addrmap[1] >> 16) &
1231 BANK_MAX_VAL_MASK) == BANK_MAX_VAL_MASK) ? 0 :
1232 (((addrmap[1] >> 16) & BANK_MAX_VAL_MASK) +
1233 BANK_B2_BASE);
1234
1235 }
1236
setup_bg_address_map(struct synps_edac_priv * priv,u32 * addrmap)1237 static void setup_bg_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1238 {
1239 priv->bankgrp_shift[0] = (addrmap[8] &
1240 BANKGRP_MAX_VAL_MASK) + BANKGRP_B0_BASE;
1241 priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) ==
1242 BANKGRP_MAX_VAL_MASK) ? 0 : (((addrmap[8] >> 8)
1243 & BANKGRP_MAX_VAL_MASK) + BANKGRP_B1_BASE);
1244
1245 }
1246
setup_rank_address_map(struct synps_edac_priv * priv,u32 * addrmap)1247 static void setup_rank_address_map(struct synps_edac_priv *priv, u32 *addrmap)
1248 {
1249 priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) ==
1250 RANK_MAX_VAL_MASK) ? 0 : ((addrmap[0] &
1251 RANK_MAX_VAL_MASK) + RANK_B0_BASE);
1252 }
1253
1254 /**
1255 * setup_address_map - Set Address Map by querying ADDRMAP registers.
1256 * @priv: DDR memory controller private instance data.
1257 *
1258 * Set Address Map by querying ADDRMAP registers.
1259 *
1260 * Return: none.
1261 */
setup_address_map(struct synps_edac_priv * priv)1262 static void setup_address_map(struct synps_edac_priv *priv)
1263 {
1264 u32 addrmap[12];
1265 int index;
1266
1267 for (index = 0; index < 12; index++) {
1268 u32 addrmap_offset;
1269
1270 addrmap_offset = ECC_ADDRMAP0_OFFSET + (index * 4);
1271 addrmap[index] = readl(priv->baseaddr + addrmap_offset);
1272 }
1273
1274 setup_row_address_map(priv, addrmap);
1275
1276 setup_column_address_map(priv, addrmap);
1277
1278 setup_bank_address_map(priv, addrmap);
1279
1280 setup_bg_address_map(priv, addrmap);
1281
1282 setup_rank_address_map(priv, addrmap);
1283 }
1284 #endif /* CONFIG_EDAC_DEBUG */
1285
1286 /**
1287 * mc_probe - Check controller and bind driver.
1288 * @pdev: platform device.
1289 *
1290 * Probe a specific controller instance for binding with the driver.
1291 *
1292 * Return: 0 if the controller instance was successfully bound to the
1293 * driver; otherwise, < 0 on error.
1294 */
mc_probe(struct platform_device * pdev)1295 static int mc_probe(struct platform_device *pdev)
1296 {
1297 const struct synps_platform_data *p_data;
1298 struct edac_mc_layer layers[2];
1299 struct synps_edac_priv *priv;
1300 struct mem_ctl_info *mci;
1301 void __iomem *baseaddr;
1302 struct resource *res;
1303 int rc;
1304
1305 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1306 baseaddr = devm_ioremap_resource(&pdev->dev, res);
1307 if (IS_ERR(baseaddr))
1308 return PTR_ERR(baseaddr);
1309
1310 p_data = of_device_get_match_data(&pdev->dev);
1311 if (!p_data)
1312 return -ENODEV;
1313
1314 if (!p_data->get_ecc_state(baseaddr)) {
1315 edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n");
1316 return -ENXIO;
1317 }
1318
1319 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
1320 layers[0].size = SYNPS_EDAC_NR_CSROWS;
1321 layers[0].is_virt_csrow = true;
1322 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1323 layers[1].size = SYNPS_EDAC_NR_CHANS;
1324 layers[1].is_virt_csrow = false;
1325
1326 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
1327 sizeof(struct synps_edac_priv));
1328 if (!mci) {
1329 edac_printk(KERN_ERR, EDAC_MC,
1330 "Failed memory allocation for mc instance\n");
1331 return -ENOMEM;
1332 }
1333
1334 priv = mci->pvt_info;
1335 priv->baseaddr = baseaddr;
1336 priv->p_data = p_data;
1337
1338 mc_init(mci, pdev);
1339
1340 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
1341 rc = setup_irq(mci, pdev);
1342 if (rc)
1343 goto free_edac_mc;
1344 }
1345
1346 rc = edac_mc_add_mc(mci);
1347 if (rc) {
1348 edac_printk(KERN_ERR, EDAC_MC,
1349 "Failed to register with EDAC core\n");
1350 goto free_edac_mc;
1351 }
1352
1353 #ifdef CONFIG_EDAC_DEBUG
1354 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) {
1355 if (edac_create_sysfs_attributes(mci)) {
1356 edac_printk(KERN_ERR, EDAC_MC,
1357 "Failed to create sysfs entries\n");
1358 goto free_edac_mc;
1359 }
1360 }
1361
1362 if (of_device_is_compatible(pdev->dev.of_node,
1363 "xlnx,zynqmp-ddrc-2.40a"))
1364 setup_address_map(priv);
1365 #endif
1366
1367 /*
1368 * Start capturing the correctable and uncorrectable errors. A write of
1369 * 0 starts the counters.
1370 */
1371 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT))
1372 writel(0x0, baseaddr + ECC_CTRL_OFST);
1373
1374 return rc;
1375
1376 free_edac_mc:
1377 edac_mc_free(mci);
1378
1379 return rc;
1380 }
1381
1382 /**
1383 * mc_remove - Unbind driver from controller.
1384 * @pdev: Platform device.
1385 *
1386 * Return: Unconditionally 0
1387 */
mc_remove(struct platform_device * pdev)1388 static int mc_remove(struct platform_device *pdev)
1389 {
1390 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
1391 struct synps_edac_priv *priv = mci->pvt_info;
1392
1393 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
1394 disable_intr(priv);
1395
1396 #ifdef CONFIG_EDAC_DEBUG
1397 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT)
1398 edac_remove_sysfs_attributes(mci);
1399 #endif
1400
1401 edac_mc_del_mc(&pdev->dev);
1402 edac_mc_free(mci);
1403
1404 return 0;
1405 }
1406
1407 static struct platform_driver synps_edac_mc_driver = {
1408 .driver = {
1409 .name = "synopsys-edac",
1410 .of_match_table = synps_edac_match,
1411 },
1412 .probe = mc_probe,
1413 .remove = mc_remove,
1414 };
1415
1416 module_platform_driver(synps_edac_mc_driver);
1417
1418 MODULE_AUTHOR("Xilinx Inc");
1419 MODULE_DESCRIPTION("Synopsys DDR ECC driver");
1420 MODULE_LICENSE("GPL v2");
1421