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Searched refs:interrupts (Results 1 – 25 of 118) sorted by relevance

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/drivers/of/unittest-data/
Dtests-interrupts.dtsi5 interrupts {
39 interrupts = <1>, <2>, <3>, <4>;
44 interrupts = <1>, <2>, <3>, <4>;
47 interrupts-extended0 {
49 interrupts-extended = <&test_intc0 1>,
62 interrupts = <1>;
68 interrupts = <1>; /* invalid specifier - too short */
Dtestcases.dts16 #include "tests-interrupts.dtsi"
/drivers/staging/gasket/
Dgasket_interrupt.c39 const struct gasket_interrupt_desc *interrupts; member
101 interrupt_data->interrupts[i].index, in gasket_interrupt_setup()
102 interrupt_data->interrupts[i].reg, in gasket_interrupt_setup()
103 interrupt_data->interrupts[i].packing); in gasket_interrupt_setup()
104 if (interrupt_data->interrupts[i].packing == UNPACKED) { in gasket_interrupt_setup()
105 value = interrupt_data->interrupts[i].index; in gasket_interrupt_setup()
107 switch (interrupt_data->interrupts[i].packing) { in gasket_interrupt_setup()
123 interrupt_data->interrupts[i].packing); in gasket_interrupt_setup()
130 interrupt_data->interrupts[i].reg); in gasket_interrupt_setup()
132 value |= interrupt_data->interrupts[i].index in gasket_interrupt_setup()
[all …]
/drivers/net/ethernet/8390/
Dlib8390.c429 int interrupts, nr_serviced = 0; in __ei_interrupt() local
456 while ((interrupts = ei_inb_p(e8390_base + EN0_ISR)) != 0 && in __ei_interrupt()
461 ei_outb_p(interrupts, e8390_base + EN0_ISR); in __ei_interrupt()
462 interrupts = 0; in __ei_interrupt()
465 if (interrupts & ENISR_OVER) in __ei_interrupt()
467 else if (interrupts & (ENISR_RX+ENISR_RX_ERR)) { in __ei_interrupt()
472 if (interrupts & ENISR_TX) in __ei_interrupt()
474 else if (interrupts & ENISR_TX_ERR) in __ei_interrupt()
477 if (interrupts & ENISR_COUNTERS) { in __ei_interrupt()
485 if (interrupts & ENISR_RDC) in __ei_interrupt()
[all …]
Daxnet_cs.c1089 int interrupts, nr_serviced = 0, i; in ax_interrupt() local
1127 while ((interrupts = inb_p(e8390_base + EN0_ISR)) != 0 && in ax_interrupt()
1130 if (!netif_running(dev) || (interrupts == 0xff)) { in ax_interrupt()
1133 outb_p(interrupts, e8390_base + EN0_ISR); in ax_interrupt()
1134 interrupts = 0; in ax_interrupt()
1140 outb_p(interrupts, e8390_base + EN0_ISR); in ax_interrupt()
1142 if (!(inb(e8390_base + EN0_ISR) & interrupts)) in ax_interrupt()
1145 outb_p(interrupts, e8390_base + EN0_ISR); in ax_interrupt()
1147 if (interrupts & ENISR_OVER) in ax_interrupt()
1149 else if (interrupts & (ENISR_RX+ENISR_RX_ERR)) in ax_interrupt()
[all …]
/drivers/acpi/acpica/
Drsirq.c27 {ACPI_RSC_BITMASK16, ACPI_RS_OFFSET(data.irq.interrupts[0]),
81 {ACPI_RSC_BITMASK16, ACPI_RS_OFFSET(data.irq.interrupts[0]),
197 {ACPI_RSC_MOVE32, ACPI_RS_OFFSET(data.extended_irq.interrupts[0]),
198 AML_OFFSET(extended_irq.interrupts[0]),
204 ACPI_RS_OFFSET(data.extended_irq.interrupts[0]),
/drivers/staging/mt7621-dts/
Dmt7621.dtsi96 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
127 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
162 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
195 interrupts = <0 13 4>;
212 interrupts = <0 11 4>;
345 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
360 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
374 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
411 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
503 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
/drivers/acpi/
Dpci_link.c107 if (!p->interrupts[i]) { in acpi_pci_link_check_possible()
110 p->interrupts[i]); in acpi_pci_link_check_possible()
113 link->irq.possible[i] = p->interrupts[i]; in acpi_pci_link_check_possible()
133 if (!p->interrupts[i]) { in acpi_pci_link_check_possible()
136 p->interrupts[i]); in acpi_pci_link_check_possible()
139 link->irq.possible[i] = p->interrupts[i]; in acpi_pci_link_check_possible()
195 *irq = p->interrupts[0]; in acpi_pci_link_check_current()
211 *irq = p->interrupts[0]; in acpi_pci_link_check_current()
312 resource->res.data.irq.interrupts[0] = irq; in acpi_pci_link_set()
330 resource->res.data.extended_irq.interrupts[0] = irq; in acpi_pci_link_set()
Devged.c91 gsi = p->interrupts[0]; in acpi_ged_request_interrupt()
93 gsi = pext->interrupts[0]; in acpi_ged_request_interrupt()
Dirq.c194 acpi_irq_parse_one_match(fwnode, irq->interrupts[ctx->index], in acpi_irq_parse_one_cb()
207 acpi_irq_parse_one_match(fwnode, eirq->interrupts[ctx->index], in acpi_irq_parse_one_cb()
/drivers/staging/fieldbus/Documentation/devicetree/bindings/fieldbus/
Darcx,anybus-controller.txt20 - interrupts : two interrupts:
24 interrupt-controller/interrupts.txt
59 interrupts = <1 IRQ_TYPE_LEVEL_LOW>, <5 IRQ_TYPE_LEVEL_LOW>;
/drivers/thermal/ti-soc-thermal/
DKconfig9 This includes alert interrupts generation and also the TSHUT
48 This includes alert interrupts generation and also the TSHUT
60 This includes alert interrupts generation and also the TSHUT
72 This includes alert interrupts generation and also the TSHUT
/drivers/pci/endpoint/
Dpci-epc-core.c251 int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts) in pci_epc_set_msi() argument
258 interrupts > 32) in pci_epc_set_msi()
264 encode_int = order_base_2(interrupts); in pci_epc_set_msi()
311 int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts) in pci_epc_set_msix() argument
317 interrupts < 1 || interrupts > 2048) in pci_epc_set_msix()
324 ret = epc->ops->set_msix(epc, func_no, interrupts - 1); in pci_epc_set_msix()
/drivers/ntb/
DKconfig21 hardware doorbells. MSI interrupts typically offer lower latency
22 than doorbells and more MSI interrupts can be made available to
24 in the hardware driver for creating the MSI interrupts.
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_mdss.c69 u32 interrupts; in dpu_mdss_irq() local
73 interrupts = readl_relaxed(dpu_mdss->mmio + HW_INTR_STATUS); in dpu_mdss_irq()
75 while (interrupts) { in dpu_mdss_irq()
76 irq_hw_number_t hwirq = fls(interrupts) - 1; in dpu_mdss_irq()
94 interrupts &= ~(1 << hwirq); in dpu_mdss_irq()
/drivers/char/tpm/
Dtpm_tis.c52 static bool interrupts = true; variable
53 module_param(interrupts, bool, 0444);
54 MODULE_PARM_DESC(interrupts, "Enable interrupts");
207 if (interrupts) in tpm_tis_init()
/drivers/gpu/drm/i915/gt/uc/
Dintel_guc.c74 guc->interrupts.reset = gen11_reset_guc_interrupts; in intel_guc_init_early()
75 guc->interrupts.enable = gen11_enable_guc_interrupts; in intel_guc_init_early()
76 guc->interrupts.disable = gen11_disable_guc_interrupts; in intel_guc_init_early()
79 guc->interrupts.reset = gen9_reset_guc_interrupts; in intel_guc_init_early()
80 guc->interrupts.enable = gen9_enable_guc_interrupts; in intel_guc_init_early()
81 guc->interrupts.disable = gen9_disable_guc_interrupts; in intel_guc_init_early()
/drivers/memory/
Demif.c1012 u32 interrupts; in emif_interrupt_handler() local
1019 interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); in emif_interrupt_handler()
1020 writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS); in emif_interrupt_handler()
1027 if (interrupts & TA_SYS_MASK) in emif_interrupt_handler()
1030 if (interrupts & ERR_SYS_MASK) in emif_interrupt_handler()
1031 dev_err(dev, "Access error from SYS port - %x\n", interrupts); in emif_interrupt_handler()
1035 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS); in emif_interrupt_handler()
1036 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS); in emif_interrupt_handler()
1038 if (interrupts & ERR_LL_MASK) in emif_interrupt_handler()
1040 interrupts); in emif_interrupt_handler()
[all …]
/drivers/uio/
DKconfig8 kernel interrupts and memory locations, allowing some drivers
32 interrupt handling code. Shared interrupts are not supported.
35 handles interrupts in a special way. Userspace is responsible
37 interrupts in the interrupt controller using the write() syscall.
46 interrupt handling code. Shared interrupts are not supported.
/drivers/pnp/pnpacpi/
Drsparser.c315 if (p->interrupts[i]) in pnpacpi_parse_irq_option()
316 __set_bit(p->interrupts[i], map.bits); in pnpacpi_parse_irq_option()
332 if (p->interrupts[i]) { in pnpacpi_parse_ext_irq_option()
333 if (p->interrupts[i] < PNP_IRQ_NR) in pnpacpi_parse_ext_irq_option()
334 __set_bit(p->interrupts[i], map.bits); in pnpacpi_parse_ext_irq_option()
338 p->interrupts[i], PNP_IRQ_NR); in pnpacpi_parse_ext_irq_option()
677 irq->interrupts[0] = p->start; in pnpacpi_encode_irq()
707 extended_irq->interrupts[0] = p->start; in pnpacpi_encode_ext_irq()
/drivers/net/phy/
Drealtek.c97 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in rtl8201_config_intr()
109 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in rtl8211b_config_intr()
122 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in rtl8211e_config_intr()
135 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in rtl8211f_config_intr()
Dlxt.c78 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in lxt970_config_intr()
102 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) in lxt971_config_intr()
/drivers/bcma/
Ddriver_mips.c171 char interrupts[25]; in bcma_core_mips_print_irq() local
172 char *ints = interrupts; in bcma_core_mips_print_irq()
178 bcma_debug(dev->bus, "core 0x%04x, irq:%s\n", dev->id.id, interrupts); in bcma_core_mips_print_irq()
/drivers/staging/axis-fifo/
Daxis-fifo.txt20 - interrupts: Should contain interrupts lines.
58 interrupts = <0 29 4>;
/drivers/irqchip/
DKconfig247 to 8 external interrupts with configurable sense select.
297 a free irq and configures the IP. Thus the peripheral interrupts are
325 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
492 interrupts and connects them to each core's local interrupt
493 controller. Aside from timer and software interrupts, all other

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