| /drivers/gpu/drm/msm/disp/ |
| D | mdp_kms.c | 24 uint32_t irqmask = mdp_kms->vblank_mask; in update_irq() local
29 irqmask |= irq->irqmask; in update_irq()
31 mdp_kms->funcs->set_irqmask(mdp_kms, irqmask, mdp_kms->cur_irq_mask); in update_irq()
32 mdp_kms->cur_irq_mask = irqmask; in update_irq()
54 if (handler->irqmask & status) { in mdp_dispatch_irqs()
56 handler->irq(handler, handler->irqmask & status); in mdp_dispatch_irqs()
87 void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask) in mdp_irq_wait() argument
92 .irqmask = irqmask, in mdp_irq_wait()
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| D | mdp_kms.h | 22 void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask,
59 uint32_t irqmask; member
66 void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask);
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| /drivers/clocksource/ |
| D | timer-atmel-st.c | 21 static u32 irqmask; variable
53 sr &= irqmask; in at91rm9200_timer_interrupt()
108 irqmask = 0; in clkevt32k_shutdown()
109 regmap_write(regmap_st, AT91_ST_IER, irqmask); in clkevt32k_shutdown()
121 irqmask = AT91_ST_ALMS; in clkevt32k_set_oneshot()
123 regmap_write(regmap_st, AT91_ST_IER, irqmask); in clkevt32k_set_oneshot()
132 irqmask = AT91_ST_PITS; in clkevt32k_set_periodic()
134 regmap_write(regmap_st, AT91_ST_IER, irqmask); in clkevt32k_set_periodic()
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| /drivers/irqchip/ |
| D | irq-i8259.c | 114 int irqmask = 1 << irq; in i8259A_irq_real() local
118 value = inb(PIC_MASTER_CMD) & irqmask; in i8259A_irq_real()
123 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); in i8259A_irq_real()
136 unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; in mask_and_ack_8259A() local
139 irqmask = 1 << irq; in mask_and_ack_8259A()
156 if (cached_irq_mask & irqmask) in mask_and_ack_8259A()
158 cached_irq_mask |= irqmask; in mask_and_ack_8259A()
191 if (!(spurious_irq_mask & irqmask)) { in mask_and_ack_8259A()
193 spurious_irq_mask |= irqmask; in mask_and_ack_8259A()
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| /drivers/gpu/drm/omapdrm/ |
| D | omap_irq.c | 14 u32 irqmask; member
23 u32 irqmask = priv->irq_mask; in omap_irq_update() local
28 irqmask |= wait->irqmask; in omap_irq_update()
30 DBG("irqmask=%08x", irqmask); in omap_irq_update()
32 priv->dispc_ops->write_irqenable(priv->dispc, irqmask); in omap_irq_update()
42 u32 irqmask, int count) in omap_irq_wait_init() argument
49 wait->irqmask = irqmask; in omap_irq_wait_init()
243 if (wait->irqmask & irqstatus) in omap_irq_handler()
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| D | omap_irq.h | 25 u32 irqmask, int count);
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| /drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4_irq.c | 13 void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, in mdp4_set_irqmask() argument
17 irqmask ^ (irqmask & old_irqmask)); in mdp4_set_irqmask()
18 mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask); in mdp4_set_irqmask()
51 error_handler->irqmask = MDP4_IRQ_PRIMARY_INTF_UDERRUN | in mdp4_irq_postinstall()
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| D | mdp4_crtc.c | 550 return mdp4_crtc->vblank.irqmask; in mdp4_crtc_vblank()
635 mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma); in mdp4_crtc_init()
638 mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma); in mdp4_crtc_init()
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| /drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_irq.c | 15 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, in mdp5_set_irqmask() argument
19 irqmask ^ (irqmask & old_irqmask)); in mdp5_set_irqmask()
20 mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask); in mdp5_set_irqmask()
58 error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN | in mdp5_irq_postinstall()
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| /drivers/gpio/ |
| D | gpio-sa1100.c | 20 u32 irqmask; member
115 grer = sgc->irqrising & sgc->irqmask; in sa1100_update_edge_regs()
116 gfer = sgc->irqfalling & sgc->irqmask; in sa1100_update_edge_regs()
162 sgc->irqmask &= ~mask; in sa1100_gpio_mask()
172 sgc->irqmask |= mask; in sa1100_gpio_unmask()
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| /drivers/net/wireless/mediatek/mt76/ |
| D | mmio.c | 74 dev->mmio.irqmask &= ~clear; in mt76_set_irq_mask()
75 dev->mmio.irqmask |= set; in mt76_set_irq_mask()
76 mt76_mmio_wr(dev, addr, dev->mmio.irqmask); in mt76_set_irq_mask()
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| D | mt76x02_mmio.c | 267 trace_dev_irq(dev, intr, dev->mt76.mmio.irqmask); in mt76x02_irq_handler()
269 intr &= dev->mt76.mmio.irqmask; in mt76x02_irq_handler()
438 u32 mask = dev->mt76.mmio.irqmask; in mt76x02_watchdog_reset()
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| /drivers/regulator/ |
| D | lp8755.c | 46 unsigned int irqmask; member
370 && (pchip->irqmask & (0x04 << icnt)) in lp8755_irq_handler()
389 if ((flag1 & 0x01) && (pchip->irqmask & 0x01)) in lp8755_irq_handler()
400 if ((flag1 & 0x02) && (pchip->irqmask & 0x02)) in lp8755_irq_handler()
432 pchip->irqmask = regval; in lp8755_int_config()
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| /drivers/ata/ |
| D | pata_hpt3x2n.c | 495 u8 irqmask; in hpt3x2n_init_one() local
544 pci_read_config_byte(dev, 0x5A, &irqmask); in hpt3x2n_init_one()
545 irqmask &= ~0x10; in hpt3x2n_init_one()
546 pci_write_config_byte(dev, 0x5a, irqmask); in hpt3x2n_init_one()
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| D | pata_icside.c | 67 unsigned int irqmask; member
384 info->irqmask = 1; in pata_icside_register_v5()
445 ec->irqmask = info->irqmask; in pata_icside_add_ports()
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| D | pata_hpt37x.c | 824 u8 irqmask; in hpt37x_init_one() local
916 pci_read_config_byte(dev, 0x5A, &irqmask); in hpt37x_init_one()
917 irqmask &= ~0x10; in hpt37x_init_one()
918 pci_write_config_byte(dev, 0x5a, irqmask); in hpt37x_init_one()
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| /drivers/media/rc/ |
| D | winbond-cir.c | 198 u8 irqmask; member
248 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) in wbcir_set_irqmask() argument
250 if (data->irqmask == irqmask) in wbcir_set_irqmask()
254 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); in wbcir_set_irqmask()
255 data->irqmask = irqmask; in wbcir_set_irqmask()
464 status &= data->irqmask; in wbcir_irq_handler()
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| /drivers/media/pci/tw5864/ |
| D | tw5864-core.c | 79 tw_writel(TW5864_INTR_ENABLE_L, dev->irqmask & 0xffff); in tw5864_irqmask_apply()
80 tw_writel(TW5864_INTR_ENABLE_H, (dev->irqmask >> 16)); in tw5864_irqmask_apply()
88 dev->irqmask = 0; in tw5864_interrupts_disable()
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| D | tw5864.h | 163 u32 irqmask; member
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc-compat.h | 13 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
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| D | dispc-compat.c | 631 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, in omap_dispc_wait_for_irq_interruptible_timeout() argument
640 irqmask); in omap_dispc_wait_for_irq_interruptible_timeout()
648 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); in omap_dispc_wait_for_irq_interruptible_timeout()
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| /drivers/net/wireless/mediatek/mt76/mt7603/ |
| D | core.c | 23 intr &= dev->mt76.mmio.irqmask; in mt7603_irq_handler()
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| /drivers/net/ethernet/nvidia/ |
| D | forcedeth.c | 783 u32 irqmask; member
3620 if (np->irqmask != NVREG_IRQMASK_CPU) { in nv_change_interrupt_mode()
3621 np->irqmask = NVREG_IRQMASK_CPU; in nv_change_interrupt_mode()
3630 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { in nv_change_interrupt_mode()
3631 np->irqmask = NVREG_IRQMASK_THROUGHPUT; in nv_change_interrupt_mode()
3653 if (!(np->events & np->irqmask)) in nv_nic_irq()
3686 if (!(np->events & np->irqmask)) in nv_nic_irq_optimized()
3715 if (!(events & np->irqmask)) in nv_nic_irq_tx()
3795 np->nic_poll_irq = np->irqmask; in nv_napi_poll()
3809 writel(np->irqmask, base + NvRegIrqMask); in nv_napi_poll()
[all …]
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| /drivers/net/wireless/mediatek/mt76/mt7615/ |
| D | pci.c | 49 intr &= dev->mt76.mmio.irqmask; in mt7615_irq_handler()
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| /drivers/media/pci/ivtv/ |
| D | ivtv-driver.c | 316 itv->irqmask &= ~mask; in ivtv_clear_irq_mask()
317 write_reg_sync(itv->irqmask, IVTV_REG_IRQMASK); in ivtv_clear_irq_mask()
322 itv->irqmask |= mask; in ivtv_set_irq_mask()
323 write_reg_sync(itv->irqmask, IVTV_REG_IRQMASK); in ivtv_set_irq_mask()
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