| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | nv40.c | 47 u32 ref = 27000, khz = 0; in read_pll_1() local
50 khz = ref * N / M; in read_pll_1()
52 return khz >> P; in read_pll_1()
66 u32 ref = 27000, khz = 0; in read_pll_2() local
69 khz = ref * N1 / M1; in read_pll_2()
72 khz = khz * N2 / M2; in read_pll_2()
74 khz = 0; in read_pll_2()
78 return khz >> P; in read_pll_2()
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, in nv40_clk_calc_pll() argument
135 if (khz < pll.vco1.max_freq) in nv40_clk_calc_pll()
[all …]
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| D | gt215.c | 187 gt215_clk_info(struct nvkm_clk *base, int idx, u32 khz, in gt215_clk_info() argument
196 switch (khz) { in gt215_clk_info()
199 return khz; in gt215_clk_info()
202 return khz; in gt215_clk_info()
205 return khz; in gt215_clk_info()
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
210 diff = ((khz + 3000) - oclk); in gt215_clk_info()
235 gt215_pll_info(struct nvkm_clk *base, int idx, u32 pll, u32 khz, in gt215_pll_info() argument
248 ret = gt215_clk_info(&clk->base, idx, khz, info); in gt215_pll_info()
249 diff = khz - ret; in gt215_pll_info()
[all …]
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| D | base.c | 285 int khz = pstate->base.domain[nv_clk_src_mem]; in nvkm_pstate_prog() local
287 ret = ram->func->calc(ram, khz); in nvkm_pstate_prog()
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| /drivers/cpufreq/ |
| D | powernow-k6.c | 157 unsigned khz; in powernow_k6_cpu_init() local
163 khz = cpu_khz; in powernow_k6_cpu_init()
165 if (khz >= usual_frequency_table[i].freq - FREQ_RANGE && in powernow_k6_cpu_init()
166 khz <= usual_frequency_table[i].freq + FREQ_RANGE) { in powernow_k6_cpu_init()
167 khz = usual_frequency_table[i].freq; in powernow_k6_cpu_init()
184 khz); in powernow_k6_cpu_init()
201 busfreq = khz / max_multiplier; in powernow_k6_cpu_init()
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| D | pxa2xx-cpufreq.c | 53 unsigned int khz; member
199 new_freq_cpu = pxa_freq_settings[idx].khz; in pxa_set_target()
246 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; in pxa_cpufreq_init()
254 pxa255_turbo_freqs[i].khz; in pxa_cpufreq_init()
263 freq = pxa27x_freqs[i].khz; in pxa_cpufreq_init()
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| D | gx-suspmod.c | 217 static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, in gx_validate_speed() argument
229 tmp_off = ((khz * i) / stock_freq) & 0xff; in gx_validate_speed()
234 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) { in gx_validate_speed()
250 static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz) in gx_set_cpuspeed() argument
259 new_khz = gx_validate_speed(khz, &gx_params->on_duration, in gx_set_cpuspeed()
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| D | longhaul.c | 110 int khz; in calc_speed() local
111 khz = (mult/10)*fsb; in calc_speed()
113 khz += fsb/2; in calc_speed()
114 khz *= 1000; in calc_speed()
115 return khz; in calc_speed()
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| D | sa1110-cpufreq.c | 122 static inline u_int ns_to_cycles(u_int ns, u_int khz) in ns_to_cycles() argument
124 return (ns * khz + 999999) / 1000000; in ns_to_cycles()
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| D | powernow-k8.c | 1124 unsigned int khz = 0; in powernowk8_get() local
1134 khz = find_khz_freq_from_fid(data->currfid); in powernowk8_get()
1138 return khz; in powernowk8_get()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 120 static void update_global_dpp_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz) in update_global_dpp_clk() argument
123 * clk_mgr->dentist_vco_freq_khz / khz; in update_global_dpp_clk()
132 static void update_display_clk(struct clk_mgr_internal *clk_mgr, unsigned int khz) in update_display_clk() argument
135 * clk_mgr->dentist_vco_freq_khz / khz; in update_display_clk()
143 static void request_voltage_and_program_disp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz) in request_voltage_and_program_disp_clk() argument
148 bool going_up = clk_mgr->base.clks.dispclk_khz < khz; in request_voltage_and_program_disp_clk()
153 clk_mgr->base.clks.dispclk_khz = khz; in request_voltage_and_program_disp_clk()
158 update_display_clk(clk_mgr, khz); in request_voltage_and_program_disp_clk()
164 …tic void request_voltage_and_program_global_dpp_clk(struct clk_mgr *clk_mgr_base, unsigned int khz) in request_voltage_and_program_global_dpp_clk() argument
169 bool going_up = clk_mgr->base.clks.dppclk_khz < khz; in request_voltage_and_program_global_dpp_clk()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | nv50.c | 198 struct nvkm_ior *ior, int id, u32 khz) in nv50_disp_super_ied_on() argument
237 data = nvbios_oclk_match(bios, iedtrs.clkcmp[id], khz); in nv50_disp_super_ied_on()
240 id, ior->asy.proto_evo, flags, khz); in nv50_disp_super_ied_on()
328 const u32 khz = head->asy.hz / 1000; in nv50_disp_super_2_2_dp() local
340 do_div(h, khz); in nv50_disp_super_2_2_dp()
346 do_div(v, khz); in nv50_disp_super_2_2_dp()
352 link_data_rate = (khz * head->asy.or.depth / 8) / ior->dp.nr; in nv50_disp_super_2_2_dp()
433 const u32 khz = head->asy.hz / 1000; in nv50_disp_super_2_2() local
462 nv50_disp_super_ied_on(head, ior, 0, khz); in nv50_disp_super_2_2()
481 const u32 khz = head->asy.hz / 1000; in nv50_disp_super_2_1() local
[all …]
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| D | dp.c | 463 u32 khz = (head->asy.hz >> ior->asy.rgdiv) / 1000; in nvkm_dp_acquire() local
464 datakbps += khz * head->asy.or.depth; in nvkm_dp_acquire()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | base.c | 38 nvkm_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 khz) in nvkm_devinit_pll_set() argument
40 return init->func->pll_set(init, type, khz); in nvkm_devinit_pll_set()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | disp.c | 166 nvbios_oclk_match(struct nvkm_bios *bios, u16 cmp, u32 khz) in nvbios_oclk_match() argument
169 if (khz / 10 >= nvbios_rd16(bios, cmp + 0x00)) in nvbios_oclk_match()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/ |
| D | devinit.h | 15 int nvkm_devinit_pll_set(struct nvkm_devinit *, u32 type, u32 khz);
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| /drivers/atm/ |
| D | zatm.h | 84 int khz; /* timer clock */ member
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| D | zatm.c | 1254 zatm_dev->khz = t2-2*t1+t0; in zatm_init()
1258 zin(VER) & uPD98401_MINOR,zatm_dev->khz/1000,zatm_dev->khz % 1000); in zatm_init()
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| /drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ |
| D | disp.h | 40 u16 nvbios_oclk_match(struct nvkm_bios *, u16 cmp, u32 khz);
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| /drivers/ata/ |
| D | pata_legacy.c | 452 int khz[4] = { 50000, 40000, 33000, 25000 }; in opti82c611a_set_piomode() local
461 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; in opti82c611a_set_piomode()
527 int khz[4] = { 50000, 40000, 33000, 25000 }; in opti82c46x_set_piomode() local
540 clock = 1000000000 / khz[sysclk]; in opti82c46x_set_piomode()
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| /drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | ramgk104.c | 962 gk104_ram_calc_data(struct gk104_ram *ram, u32 khz, struct nvkm_ram_data *data) in gk104_ram_calc_data() argument
966 u32 mhz = khz / 1000; in gk104_ram_calc_data()
972 data->freq = khz; in gk104_ram_calc_data()
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| /drivers/mmc/core/ |
| D | block.c | 978 unsigned int khz; in mmc_blk_data_timeout_ms() local
981 khz = mmc_blk_clock_khz(host); in mmc_blk_data_timeout_ms()
982 ms += DIV_ROUND_UP(data->timeout_clks, khz); in mmc_blk_data_timeout_ms()
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