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Searched refs:lane_cnt (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c100 u8 lane_cnt; member
431 ctrl->lane_cnt = lane; in edp_fill_link_cfg()
432 DBG("rate=%d lane=%d", ctrl->link_rate, ctrl->lane_cnt); in edp_fill_link_cfg()
440 data = EDP_CONFIGURATION_CTRL_LANES(ctrl->lane_cnt - 1); in edp_config_ctrl()
515 for (i = 0; i < ctrl->lane_cnt; i++) { in edp_sink_train_set_adjust()
526 for (i = 0; i < ctrl->lane_cnt; i++) { in edp_sink_train_set_adjust()
619 if (drm_dp_clock_recovery_ok(link_status, ctrl->lane_cnt)) { in edp_start_link_train_1()
676 if (drm_dp_channel_eq_ok(link_status, ctrl->lane_cnt)) { in edp_start_link_train_2()
703 lane = ctrl->lane_cnt; in edp_link_rate_down_shift()
732 ctrl->lane_cnt = lane; in edp_link_rate_down_shift()
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/drivers/media/platform/qcom/camss/
Dcamss-csid.h40 u8 lane_cnt; member
Dcamss-csid.c483 u8 num_lanes = csid->phy.lane_cnt; in csid_set_clock_rates()
687 val = phy->lane_cnt - 1; in csid_set_stream()
1264 csid->phy.lane_cnt = lane_cfg->num_data; in csid_link_setup()
/drivers/gpu/drm/i915/display/
Dintel_bios.h135 u16 lane_cnt:2; member
Dintel_dsi_vbt.c585 intel_dsi->lane_count = mipi_config->lane_cnt + 1; in intel_dsi_vbt_init()