Home
last modified time | relevance | path

Searched refs:link_rate (Results 1 – 25 of 56) sorted by relevance

123

/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_dp.c166 rate = (uint8_t) (lt_settings->link_settings.link_rate); in dpcd_set_link_settings()
174 lt_settings->link_settings.link_rate, in dpcd_set_link_settings()
472 max_lt_setting->link_settings.link_rate = in find_max_drive_settings()
473 link_training_setting->link_settings.link_rate; in find_max_drive_settings()
540 request_settings.link_settings.link_rate = in get_lane_status_and_drive_settings()
541 link_training_setting->link_settings.link_rate; in get_lane_status_and_drive_settings()
979 if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) in initialize_training_settings()
980 lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate; in initialize_training_settings()
982 lt_settings->link_settings.link_rate = link_setting->link_rate; in initialize_training_settings()
1062 char *link_rate = "Unknown"; in print_status_message() local
[all …]
Ddc_link.c565 link->cur_link_settings.link_rate = in read_edp_current_link_settings_on_detect()
571 link->cur_link_settings.link_rate = link_bw_set; in read_edp_current_link_settings_on_detect()
1484 link->cur_link_settings.link_rate != link_settings.link_rate)) { in enable_link_dp()
1494 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; in enable_link_dp()
1515 if (link_settings.link_rate == LINK_RATE_LOW) in enable_link_dp()
3049 (store_settings.link_rate != LINK_RATE_UNKNOWN)) in dc_link_set_preferred_link_settings()
3068 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN; in dc_link_set_preferred_training_settings()
3106 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */ in dc_link_bandwidth_kbps()
3146 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) in dc_link_get_link_cap()
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c101 link->cur_link_settings.link_rate, in dp_link_settings_read()
108 link->verified_link_cap.link_rate, in dp_link_settings_read()
115 link->reported_link_cap.link_rate, in dp_link_settings_read()
122 link->preferred_link_setting.link_rate, in dp_link_settings_read()
231 prefer_link_settings.link_rate = param[1]; in dp_link_settings_write()
384 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && in dp_phy_settings_write()
392 link_lane_settings.link_settings.link_rate = in dp_phy_settings_write()
393 link->preferred_link_setting.link_rate; in dp_phy_settings_write()
399 link_lane_settings.link_settings.link_rate = in dp_phy_settings_write()
400 link->cur_link_settings.link_rate; in dp_phy_settings_write()
[all …]
/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c142 intel_dp_compute_rate(intel_dp, intel_dp->link_rate, in intel_dp_link_training_clock_recovery()
257 } else if (intel_dp->link_rate == 810000) { in intel_dp_training_pattern()
272 } else if (intel_dp->link_rate >= 540000) { in intel_dp_training_pattern()
368 intel_dp->link_rate, intel_dp->lane_count); in intel_dp_start_link_train()
375 intel_dp->link_rate, intel_dp->lane_count); in intel_dp_start_link_train()
377 intel_dp->link_rate, in intel_dp_start_link_train()
Dintel_dp.h46 int link_rate, u8 lane_count,
49 int link_rate, u8 lane_count);
/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c99 u8 link_rate; member
220 (unsigned long)ctrl->link_rate * 27000000); in edp_clk_enable()
222 (unsigned long)ctrl->link_rate * 27000000); in edp_clk_enable()
416 ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate); in edp_fill_link_cfg()
422 lrate *= ctrl->link_rate; in edp_fill_link_cfg()
432 DBG("rate=%d lane=%d", ctrl->link_rate, ctrl->lane_cnt); in edp_fill_link_cfg()
702 rate = ctrl->link_rate; in edp_link_rate_down_shift()
731 ctrl->link_rate = rate; in edp_link_rate_down_shift()
763 dp_link.rate = drm_dp_bw_code_to_link_rate(ctrl->link_rate); in edp_do_link_train()
846 if (ctrl->link_rate == DP_LINK_BW_1_62) { in edp_sw_mvid_nvid()
[all …]
/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c271 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); in analogix_dp_link_start()
275 buf[0] = dp->link_train.link_rate; in analogix_dp_link_start()
576 dp->link_train.link_rate = reg; in analogix_dp_process_equalizer_training()
578 dp->link_train.link_rate); in analogix_dp_process_equalizer_training()
652 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); in analogix_dp_full_link_train()
655 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && in analogix_dp_full_link_train()
656 (dp->link_train.link_rate != DP_LINK_BW_2_7) && in analogix_dp_full_link_train()
657 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { in analogix_dp_full_link_train()
659 dp->link_train.link_rate); in analogix_dp_full_link_train()
660 dp->link_train.link_rate = DP_LINK_BW_1_62; in analogix_dp_full_link_train()
[all …]
Danalogix_dp_core.h150 u8 link_rate; member
/drivers/gpu/drm/rockchip/
Dcdn-dp-reg.c635 u32 val, link_rate, rem; in cdn_dp_config_video() local
642 link_rate = dp->link.rate / 1000; in cdn_dp_config_video()
662 do_div(symbol, dp->link.num_lanes * link_rate * 8); in cdn_dp_config_video()
669 link_rate); in cdn_dp_config_video()
682 val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; in cdn_dp_config_video()
683 val /= (dp->link.num_lanes * link_rate); in cdn_dp_config_video()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c157 cfg->link_settings.link_rate = in dce110_fill_display_configs()
158 stream->link->cur_link_settings.link_rate; in dce110_fill_display_configs()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_link_encoder.c221 switch (link_settings->link_rate) { in update_cfg_data()
236 __func__, link_settings->link_rate); in update_cfg_data()
Ddcn20_stream_encoder.c456 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { in enc2_stream_encoder_dp_unblank()
473 param->link_settings.link_rate in enc2_stream_encoder_dp_unblank()
/drivers/scsi/hisi_sas/
Dhisi_sas_v2_hw.c2635 u32 port_id, link_rate; in phy_up_v2_hw() local
2655 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> in phy_up_v2_hw()
2660 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); in phy_up_v2_hw()
2661 link_rate = (link_rate >> (phy_no * 4)) & 0xf; in phy_up_v2_hw()
2676 sas_phy->linkrate = link_rate; in phy_up_v2_hw()
2679 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); in phy_up_v2_hw()
3200 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate; in sata_int_v2_hw() local
3241 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> in sata_int_v2_hw()
3246 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); in sata_int_v2_hw()
3247 link_rate = (link_rate >> (phy_no * 4)) & 0xf; in sata_int_v2_hw()
[all …]
Dhisi_sas_v1_hw.c1326 u32 irq_value, context, port_id, link_rate; in int_phyup_v1_hw() local
1362 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); in int_phyup_v1_hw()
1363 link_rate = (link_rate >> (phy_no * 4)) & 0xf; in int_phyup_v1_hw()
1364 sas_phy->linkrate = link_rate; in int_phyup_v1_hw()
1369 phy_no, link_rate); in int_phyup_v1_hw()
Dhisi_sas_v3_hw.c1439 u32 context, port_id, link_rate; in phy_up_v3_hw() local
1450 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); in phy_up_v3_hw()
1451 link_rate = (link_rate >> (phy_no * 4)) & 0xf; in phy_up_v3_hw()
1458 sas_phy->linkrate = link_rate; in phy_up_v3_hw()
1469 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); in phy_up_v3_hw()
1500 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); in phy_up_v3_hw()
/drivers/scsi/isci/
Dphy.c127 u32 llctl, link_rate; in sci_phy_link_layer_initialization() local
272 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3; in sci_phy_link_layer_initialization()
275 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2; in sci_phy_link_layer_initialization()
278 link_rate = SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1; in sci_phy_link_layer_initialization()
281 llctl |= SCU_SAS_LLCTL_GEN_VAL(MAX_LINK_RATE, link_rate); in sci_phy_link_layer_initialization()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_link_encoder.c971 cntl.pixel_clock = link_settings->link_rate in dcn10_link_encoder_enable_dp_output()
1010 cntl.pixel_clock = link_settings->link_rate in dcn10_link_encoder_enable_dp_mst_output()
1093 cntl.pixel_clock = link_settings->link_settings.link_rate * in dcn10_link_encoder_dp_set_lane_settings()
1105 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { in dcn10_link_encoder_dp_set_lane_settings()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_link_encoder.c1009 cntl.pixel_clock = link_settings->link_rate in dce110_link_encoder_enable_dp_output()
1048 cntl.pixel_clock = link_settings->link_rate in dce110_link_encoder_enable_dp_mst_output()
1127 cntl.pixel_clock = link_settings->link_settings.link_rate * in dce110_link_encoder_dp_set_lane_settings()
1139 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { in dce110_link_encoder_dp_set_lane_settings()
Ddce_dmcu.h238 unsigned int link_rate:4; /*[19:16]*/ member
Ddce_clk_mgr.c529 cfg->link_settings.link_rate = in dce110_fill_display_configs()
530 stream->link->cur_link_settings.link_rate; in dce110_fill_display_configs()
/drivers/scsi/mpt3sas/
Dmpt3sas_transport.c90 _transport_convert_phy_link_rate(u8 link_rate) in _transport_convert_phy_link_rate() argument
94 switch (link_rate) { in _transport_convert_phy_link_rate()
966 u64 sas_address, u16 handle, u8 phy_number, u8 link_rate) in mpt3sas_transport_update_links() argument
985 if (handle && (link_rate >= MPI2_SAS_NEG_LINK_RATE_1_5)) { in mpt3sas_transport_update_links()
996 _transport_convert_phy_link_rate(link_rate); in mpt3sas_transport_update_links()
1004 link_rate, phy_number, handle, (unsigned long long) in mpt3sas_transport_update_links()
Dmpt3sas_scsih.c5456 u8 link_rate; in _scsih_sas_host_refresh() local
5478 link_rate = sas_iounit_pg0->PhyData[i].NegotiatedLinkRate >> 4; in _scsih_sas_host_refresh()
5485 if (attached_handle && link_rate < MPI2_SAS_NEG_LINK_RATE_1_5) in _scsih_sas_host_refresh()
5486 link_rate = MPI2_SAS_NEG_LINK_RATE_1_5; in _scsih_sas_host_refresh()
5488 attached_handle, i, link_rate); in _scsih_sas_host_refresh()
5930 u64 parent_sas_address, u16 handle, u8 phy_number, u8 link_rate) in _scsih_check_device() argument
6236 u8 link_rate, prev_link_rate; in _scsih_sas_topology_change_event_debug() local
6289 link_rate = event_data->PHY[i].LinkRate >> 4; in _scsih_sas_topology_change_event_debug()
6293 handle, status_str, link_rate, prev_link_rate); in _scsih_sas_topology_change_event_debug()
6316 u8 link_rate, prev_link_rate; in _scsih_sas_topology_change_event() local
[all …]
/drivers/gpu/drm/amd/display/include/
Dbios_parser_types.h118 enum dc_link_rate link_rate; member
/drivers/atm/
Dhe.c568 rate = he_dev->atm_dev->link_rate; in he_init_cs_block()
682 rate = he_dev->atm_dev->link_rate; in he_init_cs_block_rcm()
738 (he_dev->atm_dev->link_rate * 2); in he_init_cs_block_rcm()
741 mult = he_dev->atm_dev->link_rate / ATM_OC3_PCR; in he_init_cs_block_rcm()
1095 he_dev->atm_dev->link_rate = he_is622(he_dev) ? in he_start()
2157 pcr_goal = he_dev->atm_dev->link_rate; in he_open()
2200 > (he_dev->atm_dev->link_rate * 9 / 10)) in he_open()
2780 he_dev->total_bw, he_dev->atm_dev->link_rate * 10 / 9); in he_proc_read()
/drivers/scsi/pm8001/
Dpm80xx_hwi.c2893 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28); in hw_event_port_recover() local
2904 pm8001_get_lrate_mode(phy, link_rate); in hw_event_port_recover()
2924 u8 link_rate = in hw_event_sas_phy_up() local
2942 port_id, phy_id, link_rate, portstate, deviceType)); in hw_event_sas_phy_up()
2954 pm8001_get_lrate_mode(phy, link_rate); in hw_event_sas_phy_up()
2960 pm8001_get_lrate_mode(phy, link_rate); in hw_event_sas_phy_up()
2966 pm8001_get_lrate_mode(phy, link_rate); in hw_event_sas_phy_up()
3006 u8 link_rate = in hw_event_sata_phy_up() local
3020 port_id, phy_id, link_rate, portstate)); in hw_event_sata_phy_up()
3025 pm8001_get_lrate_mode(phy, link_rate); in hw_event_sata_phy_up()

123