| /drivers/gpu/drm/amd/powerplay/ |
| D | navi10_ppt.c | 1215 uint32_t *mclk_mask, in navi10_get_profiling_clk_mask() argument
1225 if (mclk_mask) in navi10_get_profiling_clk_mask()
1226 *mclk_mask = 0; in navi10_get_profiling_clk_mask()
1235 if(mclk_mask) { in navi10_get_profiling_clk_mask()
1239 *mclk_mask = level_count - 1; in navi10_get_profiling_clk_mask()
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| D | arcturus_ppt.c | 1292 uint32_t *mclk_mask, in arcturus_get_profiling_clk_mask() argument
1309 *mclk_mask = 0; in arcturus_get_profiling_clk_mask()
1316 *mclk_mask = ARCTURUS_UMD_PSTATE_MCLK_LEVEL; in arcturus_get_profiling_clk_mask()
1323 *mclk_mask = 0; in arcturus_get_profiling_clk_mask()
1326 *mclk_mask = mem_dpm_table->count - 1; in arcturus_get_profiling_clk_mask()
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| D | amdgpu_smu.c | 1572 uint32_t sclk_mask, mclk_mask, soc_mask; in smu_default_set_performance_level() local
1590 &mclk_mask, in smu_default_set_performance_level()
1595 smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); in smu_default_set_performance_level()
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| D | vega20_ppt.c | 1989 uint32_t *mclk_mask, in vega20_get_profiling_clk_mask() argument
2005 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2012 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; in vega20_get_profiling_clk_mask()
2019 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2022 *mclk_mask = mem_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
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| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 1583 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1591 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1598 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL; in vega12_get_profiling_clk_mask()
1605 *mclk_mask = 0; in vega12_get_profiling_clk_mask()
1608 *mclk_mask = mem_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1638 uint32_t mclk_mask = 0; in vega12_dpm_force_dpm_level() local
1655 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
1659 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega12_dpm_force_dpm_level()
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| D | vega20_hwmgr.c | 2474 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2482 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2489 *mclk_mask = VEGA20_UMD_PSTATE_MCLK_LEVEL; in vega20_get_profiling_clk_mask()
2496 *mclk_mask = 0; in vega20_get_profiling_clk_mask()
2499 *mclk_mask = mem_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2673 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2692 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2696 vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); in vega20_dpm_force_dpm_level()
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| D | smu7_hwmgr.c | 2728 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) in smu7_get_profiling_clk() argument
2746 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
2749 *mclk_mask = golden_dpm_table->mclk_table.count - 2; in smu7_get_profiling_clk()
2791 *mclk_mask = 0; in smu7_get_profiling_clk()
2793 *mclk_mask = golden_dpm_table->mclk_table.count - 1; in smu7_get_profiling_clk()
2807 uint32_t mclk_mask = 0; in smu7_force_dpm_level() local
2811 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
2827 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); in smu7_force_dpm_level()
2831 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in smu7_force_dpm_level()
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| D | vega10_hwmgr.c | 4032 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4042 *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; in vega10_get_profiling_clk_mask()
4050 *mclk_mask = 0; in vega10_get_profiling_clk_mask()
4054 *mclk_mask = table_info->vdd_dep_on_mclk->count - 1; in vega10_get_profiling_clk_mask()
4142 uint32_t mclk_mask = 0; in vega10_dpm_force_dpm_level() local
4146 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4162 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4166 vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); in vega10_dpm_force_dpm_level()
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| /drivers/gpu/drm/amd/powerplay/inc/ |
| D | amdgpu_smu.h | 443 uint32_t *mclk_mask,
674 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \ argument
675 … (smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : …
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