Home
last modified time | relevance | path

Searched refs:mpcc_inst (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_mpc.c327 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc1_init_mpcc() argument
329 mpcc->mpcc_id = mpcc_inst; in mpc1_init_mpcc()
433 int mpcc_inst, in mpc1_read_mpcc_state() argument
438 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc1_read_mpcc_state()
439 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc1_read_mpcc_state()
440 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); in mpc1_read_mpcc_state()
441 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, in mpc1_read_mpcc_state()
445 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, in mpc1_read_mpcc_state()
Ddcn10_hw_sequencer.c995 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in hwss1_plane_atomic_disconnect()
1151 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn10_init_pipes()
1158 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_init_pipes()
2871 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) in get_hubp_by_inst() argument
2876 if (res_pool->hubps[i]->inst == mpcc_inst) in get_hubp_by_inst()
2888 int mpcc_inst; in dcn10_wait_for_mpcc_disconnect() local
2897 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { in dcn10_wait_for_mpcc_disconnect()
2898 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { in dcn10_wait_for_mpcc_disconnect()
2899 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
2901 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
[all …]
Ddcn10_mpc.h192 int mpcc_inst,
Ddcn10_resource.c1113 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_idle_pipe_for_layer()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dmpc.h150 int mpcc_inst,
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mpc.c468 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc2_init_mpcc() argument
470 mpcc->mpcc_id = mpcc_inst; in mpc2_init_mpcc()
Ddcn20_hwseq.c2066 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn20_fpga_init_hw()
2076 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn20_fpga_init_hw()
Ddcn20_resource.c1627 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1707 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in dcn20_split_stream_for_mpc()
2845 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn20_acquire_idle_pipe_for_layer()
/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h264 uint8_t mpcc_inst; member
/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c1219 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_split_pipe()
1624 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_free_pipe()
1895 pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst; in acquire_resource_from_hw_enabled_state()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c528 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in split_stream_across_pipes()