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/drivers/crypto/hisilicon/
Dqm.c278 void (*hw_error_init)(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,
981 static void qm_hw_error_init_v1(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe, in qm_hw_error_init_v1() argument
990 static void qm_hw_error_init_v2(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe, in qm_hw_error_init_v2() argument
993 u32 irq_enable = ce | nfe | fe | msi; in qm_hw_error_init_v2()
996 qm->error_mask = ce | nfe | fe; in qm_hw_error_init_v2()
1002 writel(nfe, qm->io_base + QM_RAS_NFE_ENABLE); in qm_hw_error_init_v2()
1861 void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe, in hisi_qm_hw_error_init() argument
1870 qm->ops->hw_error_init(qm, ce, nfe, fe, msi); in hisi_qm_hw_error_init()
Dqm.h210 void hisi_qm_hw_error_init(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe,