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Searched refs:num_slices_v (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dsc.c179 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v); in dsc_config_log()
314 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); in dsc_prepare_config()
325 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || in dsc_prepare_config()
343 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; in dsc_prepare_config()
355 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; in dsc_prepare_config()
357 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); in dsc_prepare_config()
358 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { in dsc_prepare_config()
359 …ivisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); in dsc_prepare_config()
541 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); in dsc_write_to_registers()
Ddcn20_dsc.h546 uint32_t num_slices_v; member
/drivers/gpu/drm/amd/display/dc/
Ddc_hw_types.h767 uint32_t num_slices_v; /* Number of DSC slices - vertical */ member
/drivers/gpu/drm/amd/display/dc/core/
Ddc_stream.c114 stream->timing.dsc_cfg.num_slices_v = 0; in construct()
Ddc.c1855 update->dsc_config->num_slices_v != 0); in copy_stream_update_to_stream()
/drivers/gpu/drm/amd/display/dc/dsc/
Ddc_dsc.c695 dsc_cfg->num_slices_v = pic_height/slice_height; in setup_dsc_config()