Searched refs:num_states (Results 1 – 12 of 12) sorted by relevance
/drivers/gpu/drm/amd/display/dc/dcn20/ |
D | dcn20_resource.c | 231 .num_states = 5, 2353 if (vlevel <= context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw() 2356 vlevel = context->bw_ctx.dml.soc.num_states + 1; in dcn20_fast_validate_bw() 2360 if (vlevel > context->bw_ctx.dml.soc.num_states && odm_capable) in dcn20_fast_validate_bw() 2363 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw() 2409 for (; vlevel_unsplit <= context->bw_ctx.dml.soc.num_states; vlevel_unsplit++) in dcn20_fast_validate_bw() 2459 …if (avoid_split && vlevel_unsplit <= context->bw_ctx.dml.soc.num_states && !force_split && !need_s… in dcn20_fast_validate_bw() 2499 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw() 2766 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn20_validate_bandwidth_internal() 2988 for (i = 0; i < bb->num_states; i++) { in cap_soc_clocks() [all …]
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/drivers/gpu/drm/amd/amdgpu/ |
D | amdgpu_socbb.h | 78 uint32_t num_states; member
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/drivers/gpu/drm/amd/display/dc/ |
D | dm_pp_smu.h | 236 unsigned int *clock_values_in_khz, unsigned int *num_states);
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/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
D | display_mode_vba_20.c | 1259 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() 2596 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() 3438 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull() 3520 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull() 3871 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull() 3886 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull() 3893 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull() 3961 if (i != mode_lib->vba.soc.num_states) { in dml20_ModeSupportAndSystemConfigurationFull() 3993 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull() 4010 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull() [all …]
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D | display_mode_vba_20v2.c | 1318 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() 2628 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() 3470 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull() 3552 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull() 3903 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull() 3918 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull() 3925 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull() 3993 if (i != mode_lib->vba.soc.num_states) { in dml20v2_ModeSupportAndSystemConfigurationFull() 4025 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull() 4042 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull() [all …]
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/drivers/gpu/drm/amd/display/dc/dcn21/ |
D | dcn21_resource.c | 265 .num_states = 5 956 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel() 1099 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn21_validate_bandwidth() 1281 dcn2_1_soc.num_states = 0; in update_bw_bounding_box() 1291 dcn2_1_soc.num_states++; in update_bw_bounding_box()
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/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
D | display_mode_vba_21.c | 1638 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() 3542 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull() 3584 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull() 3938 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull() 3958 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull() 3965 && i == mode_lib->vba.soc.num_states) in dml21_ModeSupportAndSystemConfigurationFull() 4033 if (i != mode_lib->vba.soc.num_states) { in dml21_ModeSupportAndSystemConfigurationFull() 4065 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull() 4082 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull() 4114 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml21_ModeSupportAndSystemConfigurationFull() [all …]
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/drivers/gpu/drm/amd/display/dc/dml/ |
D | display_mode_structs.h | 110 unsigned int num_states; member
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D | display_mode_vba.c | 235 for (i = 0; i < mode_lib->vba.soc.num_states; i++) in fetch_socbb_params() 253 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in fetch_socbb_params()
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/drivers/gpu/drm/amd/powerplay/inc/ |
D | amdgpu_smu.h | 457 int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states); 755 #define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \ argument 756 …_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
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/drivers/gpu/drm/amd/display/amdgpu_dm/ |
D | amdgpu_dm_pp_smu.c | 886 unsigned int *clock_values_in_khz, unsigned int *num_states) in pp_nv_get_uclk_dpm_states() argument 899 clock_values_in_khz, num_states)) in pp_nv_get_uclk_dpm_states()
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/drivers/gpu/drm/amd/powerplay/ |
D | navi10_ppt.c | 1427 … navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states) in navi10_get_uclk_dpm_states() argument 1435 if (!clocks_in_khz || !num_states || !table_context->driver_pptable) in navi10_get_uclk_dpm_states() 1445 *num_states = num_discrete_levels; in navi10_get_uclk_dpm_states()
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