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Searched refs:outreg (Results 1 – 12 of 12) sorted by relevance

/drivers/video/fbdev/mb862xx/
Dmb862xxfbdrv.c98 outreg(disp, GC_L0PAL0 + (regno * 4), val); in mb862xxfb_setcolreg()
215 outreg(disp, GC_DCM1, reg); in mb862xxfb_set_par()
222 outreg(disp, GC_DCM1, reg); in mb862xxfb_set_par()
230 outreg(disp, GC_L0M, reg); in mb862xxfb_set_par()
234 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24); in mb862xxfb_set_par()
236 outreg(disp, GC_WY_WX, 0); in mb862xxfb_set_par()
238 outreg(disp, GC_WH_WW, reg); in mb862xxfb_set_par()
239 outreg(disp, GC_L0OA0, 0); in mb862xxfb_set_par()
240 outreg(disp, GC_L0DA0, 0); in mb862xxfb_set_par()
241 outreg(disp, GC_L0DY_L0DX, 0); in mb862xxfb_set_par()
[all …]
Dmb862xx-i2c.c36 outreg(i2c, GC_I2C_DAR, addr); in mb862xx_i2c_do_address()
37 outreg(i2c, GC_I2C_CCR, I2C_CLOCK_AND_ENABLE); in mb862xx_i2c_do_address()
38 outreg(i2c, GC_I2C_BCR, par->i2c_rs ? I2C_REPEATED_START : I2C_START); in mb862xx_i2c_do_address()
49 outreg(i2c, GC_I2C_DAR, byte); in mb862xx_i2c_write_byte()
50 outreg(i2c, GC_I2C_BCR, I2C_START); in mb862xx_i2c_write_byte()
60 outreg(i2c, GC_I2C_BCR, I2C_START | (last ? 0 : I2C_ACK)); in mb862xx_i2c_read_byte()
71 outreg(i2c, GC_I2C_BCR, I2C_STOP); in mb862xx_i2c_stop()
72 outreg(i2c, GC_I2C_CCR, I2C_DISABLE); in mb862xx_i2c_stop()
Dmb862xxfb_accel.c33 outreg(geo, GDC_GEO_REG_INPUT_FIFO, data[total]); in mb862xxfb_write_fifo()
315 outreg(disp, GC_L0EM, 3); in mb862xxfb_init_accel()
320 outreg(draw, GDC_REG_DRAW_BASE, 0); in mb862xxfb_init_accel()
321 outreg(draw, GDC_REG_MODE_MISC, 0x8000); in mb862xxfb_init_accel()
322 outreg(draw, GDC_REG_X_RESOLUTION, xres); in mb862xxfb_init_accel()
Dmb862xxfb.h115 #define outreg(type, off, val) \ macro
/drivers/media/dvb-frontends/
Ddib7000p.c175 u16 outreg, fifo_threshold, smo_mode; in dib7000p_set_output_mode() local
177 outreg = 0; in dib7000p_set_output_mode()
185 outreg = (1 << 10); /* 0x0400 */ in dib7000p_set_output_mode()
188 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ in dib7000p_set_output_mode()
191 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0480 */ in dib7000p_set_output_mode()
195 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ in dib7000p_set_output_mode()
197 outreg = (1 << 11); in dib7000p_set_output_mode()
202 outreg = (1 << 10) | (5 << 6); in dib7000p_set_output_mode()
205 outreg = (1 << 10) | (3 << 6); in dib7000p_set_output_mode()
208 outreg = 0; in dib7000p_set_output_mode()
[all …]
Ddib7000m.c154 u16 outreg, fifo_threshold, smo_mode, in dib7000m_set_output_mode() local
157 outreg = 0; in dib7000m_set_output_mode()
165 outreg = (1 << 10); /* 0x0400 */ in dib7000m_set_output_mode()
168 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ in dib7000m_set_output_mode()
171 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ in dib7000m_set_output_mode()
175 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ in dib7000m_set_output_mode()
182 outreg = (1 << 10) | (5 << 6); in dib7000m_set_output_mode()
185 outreg = 0; in dib7000m_set_output_mode()
197 ret |= dib7000m_write_word(state, 1795, outreg); in dib7000m_set_output_mode()
Ddib8000.c408 u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */ in dib8000_set_output_mode() local
411 outreg = 0; in dib8000_set_output_mode()
420 outreg = (1 << 10); /* 0x0400 */ in dib8000_set_output_mode()
423 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ in dib8000_set_output_mode()
426 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ in dib8000_set_output_mode()
430 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ in dib8000_set_output_mode()
438 outreg = (1 << 10) | (5 << 6); in dib8000_set_output_mode()
441 outreg = 0; in dib8000_set_output_mode()
445 outreg = (1 << 10) | (3 << 6); in dib8000_set_output_mode()
460 dib8000_write_word(state, 1286, outreg); in dib8000_set_output_mode()
[all …]
Ddib3000mc.c188 u16 outreg = 0; in dib3000mc_set_output_mode() local
236 outreg = dib3000mc_read_word(state, 244) & 0x07FF; in dib3000mc_set_output_mode()
237 outreg |= (outmode << 11); in dib3000mc_set_output_mode()
238 ret |= dib3000mc_write_word(state, 244, outreg); in dib3000mc_set_output_mode()
Ddib9000.c1539 u16 outreg, smo_mode; in dib9000_fw_set_output_mode() local
1545 outreg = (1 << 10); /* 0x0400 */ in dib9000_fw_set_output_mode()
1548 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ in dib9000_fw_set_output_mode()
1551 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ in dib9000_fw_set_output_mode()
1554 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ in dib9000_fw_set_output_mode()
1557 outreg = (1 << 10) | (5 << 6); in dib9000_fw_set_output_mode()
1560 outreg = 0; in dib9000_fw_set_output_mode()
1567 dib9000_write_word(state, 1795, outreg); in dib9000_fw_set_output_mode()
1581 outreg = to_fw_output_mode(mode); in dib9000_fw_set_output_mode()
1582 return dib9000_mbx_send(state, OUT_MSG_SET_OUTPUT_MODE, &outreg, 1); in dib9000_fw_set_output_mode()
/drivers/watchdog/
Deurotechwdt.c441 goto outreg; in eurwdt_init()
462 outreg: in eurwdt_init()
Dwdt.c613 goto outreg; in wdt_init()
652 outreg: in wdt_init()
/drivers/gpio/
Dgpio-pca953x.c384 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, in pca953x_gpio_direction_output() local
391 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); in pca953x_gpio_direction_output()
428 u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off, in pca953x_gpio_set_value() local
433 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); in pca953x_gpio_set_value()