| /drivers/clk/tegra/ |
| D | clk-tegra124.c | 135 { .pdiv = 1, .hw_val = 0 },
136 { .pdiv = 2, .hw_val = 1 },
137 { .pdiv = 3, .hw_val = 2 },
138 { .pdiv = 4, .hw_val = 3 },
139 { .pdiv = 5, .hw_val = 4 },
140 { .pdiv = 6, .hw_val = 5 },
141 { .pdiv = 8, .hw_val = 6 },
142 { .pdiv = 10, .hw_val = 7 },
143 { .pdiv = 12, .hw_val = 8 },
144 { .pdiv = 16, .hw_val = 9 },
[all …]
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| D | clk-tegra114.c | 149 { .pdiv = 1, .hw_val = 0 },
150 { .pdiv = 2, .hw_val = 1 },
151 { .pdiv = 3, .hw_val = 2 },
152 { .pdiv = 4, .hw_val = 3 },
153 { .pdiv = 5, .hw_val = 4 },
154 { .pdiv = 6, .hw_val = 5 },
155 { .pdiv = 8, .hw_val = 6 },
156 { .pdiv = 10, .hw_val = 7 },
157 { .pdiv = 12, .hw_val = 8 },
158 { .pdiv = 16, .hw_val = 9 },
[all …]
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| D | clk-tegra210.c | 1388 pllx->params->pdiv_tohw[cfg->p].pdiv / 1000); in tegra210_pllx_dyn_ramp()
1409 u32 pdiv; in tegra210_pll_fixed_mdiv_cfg() local
1416 p = params->round_p_to_pdiv(p, &pdiv); in tegra210_pll_fixed_mdiv_cfg()
1503 { .pdiv = 1, .hw_val = 0 },
1504 { .pdiv = 2, .hw_val = 1 },
1505 { .pdiv = 3, .hw_val = 2 },
1506 { .pdiv = 4, .hw_val = 3 },
1507 { .pdiv = 5, .hw_val = 4 },
1508 { .pdiv = 6, .hw_val = 5 },
1509 { .pdiv = 8, .hw_val = 6 },
[all …]
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| D | clk-pll.c | 476 while (p_tohw->pdiv) { in _p_div_to_hw()
477 if (p_div <= p_tohw->pdiv) in _p_div_to_hw()
497 while (p_tohw->pdiv) { in _hw_to_p_div()
499 return p_tohw->pdiv; in _hw_to_p_div()
847 int pdiv; in clk_pll_recalc_rate() local
870 pdiv = 1; in clk_pll_recalc_rate()
872 pdiv = _hw_to_p_div(hw, cfg.p); in clk_pll_recalc_rate()
873 if (pdiv < 0) { in clk_pll_recalc_rate()
876 pdiv = 1; in clk_pll_recalc_rate()
883 cfg.m *= pdiv; in clk_pll_recalc_rate()
[all …]
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| /drivers/clk/samsung/ |
| D | clk-pll.c | 109 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
114 pdiv = (pll_con >> PLL2126_PDIV_SHIFT) & PLL2126_PDIV_MASK; in samsung_pll2126_recalc_rate()
118 do_div(fvco, (pdiv + 2) << sdiv); in samsung_pll2126_recalc_rate()
142 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
147 pdiv = (pll_con >> PLL3000_PDIV_SHIFT) & PLL3000_PDIV_MASK; in samsung_pll3000_recalc_rate()
151 do_div(fvco, pdiv << sdiv); in samsung_pll3000_recalc_rate()
179 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
184 pdiv = (pll_con >> PLL35XX_PDIV_SHIFT) & PLL35XX_PDIV_MASK; in samsung_pll35xx_recalc_rate()
188 do_div(fvco, (pdiv << sdiv)); in samsung_pll35xx_recalc_rate()
201 return (rate->mdiv != old_mdiv || rate->pdiv != old_pdiv); in samsung_pll35xx_mp_change()
[all …]
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| D | clk-pll.h | 51 .pdiv = (_p), \
60 .pdiv = (_p), \
69 .pdiv = (_p), \
78 .pdiv = (_p), \
88 .pdiv = (_p), \
98 .pdiv = (_p), \
109 .pdiv = (_p), \
121 unsigned int pdiv; member
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| /drivers/cpufreq/ |
| D | s3c2412-cpufreq.c | 42 unsigned int hdiv, pdiv, armdiv, dvs; in s3c2412_cpufreq_calcdivs() local
90 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2412_cpufreq_calcdivs()
92 if ((hclk / pdiv) > cfg->max.pclk) in s3c2412_cpufreq_calcdivs()
93 pdiv++; in s3c2412_cpufreq_calcdivs()
95 cfg->freq.pclk = hclk / pdiv; in s3c2412_cpufreq_calcdivs()
97 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); in s3c2412_cpufreq_calcdivs()
99 if (pdiv > 2) in s3c2412_cpufreq_calcdivs()
102 pdiv *= hdiv; in s3c2412_cpufreq_calcdivs()
107 cfg->divs.p_divisor = pdiv * armdiv; in s3c2412_cpufreq_calcdivs()
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| D | s3c2440-cpufreq.c | 56 unsigned int hdiv, pdiv; in s3c2440_cpufreq_calcdivs() local
90 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2440_cpufreq_calcdivs()
92 if ((hclk / pdiv) > cfg->max.pclk) in s3c2440_cpufreq_calcdivs()
93 pdiv++; in s3c2440_cpufreq_calcdivs()
95 s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv); in s3c2440_cpufreq_calcdivs()
97 if (pdiv > 2) in s3c2440_cpufreq_calcdivs()
100 pdiv *= hdiv; in s3c2440_cpufreq_calcdivs()
121 cfg->divs.p_divisor = pdiv; in s3c2440_cpufreq_calcdivs()
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| D | s3c2410-cpufreq.c | 46 unsigned int hdiv, pdiv; in s3c2410_cpufreq_calcdivs() local
65 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
66 pclk = hclk / pdiv; in s3c2410_cpufreq_calcdivs()
73 pdiv *= hdiv; in s3c2410_cpufreq_calcdivs()
76 cfg->divs.p_divisor = pdiv; in s3c2410_cpufreq_calcdivs()
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| D | brcmstb-avs-cpufreq.c | 318 static void brcm_avs_parse_p1(u32 p1, unsigned int *mdiv_p0, unsigned int *pdiv, in brcm_avs_parse_p1() argument
322 *pdiv = (p1 >> PDIV_SHIFT) & PDIV_MASK; in brcm_avs_parse_p1()
638 unsigned int ndiv, pdiv; in show_brcm_avs_pmap() local
644 brcm_avs_parse_p1(pmap.p1, &mdiv_p0, &pdiv, &ndiv); in show_brcm_avs_pmap()
648 pmap.p1, pmap.p2, ndiv, pdiv, mdiv_p0, mdiv_p1, mdiv_p2, in show_brcm_avs_pmap()
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| /drivers/clk/ |
| D | clk-cdce925.c | 68 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */ member
289 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) in cdce925_clk_set_pdiv() argument
295 0x03, (pdiv >> 8) & 0x03); in cdce925_clk_set_pdiv()
296 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); in cdce925_clk_set_pdiv()
299 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); in cdce925_clk_set_pdiv()
302 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); in cdce925_clk_set_pdiv()
305 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); in cdce925_clk_set_pdiv()
308 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); in cdce925_clk_set_pdiv()
311 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv); in cdce925_clk_set_pdiv()
314 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv); in cdce925_clk_set_pdiv()
[all …]
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| /drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 114 vco_out->pdiv = 1; in pll_calc_param()
292 unsigned int pdiv; in pll_fractional_change_only() local
306 val = readl(pll->control_base + ctrl->pdiv.offset); in pll_fractional_change_only()
307 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); in pll_fractional_change_only()
309 if (pdiv != vco->pdiv) in pll_fractional_change_only()
331 if (vco->pdiv == 0) in pll_set_rate()
334 ref_freq = parent_rate / vco->pdiv; in pll_set_rate()
421 val = readl(pll->control_base + ctrl->pdiv.offset); in pll_set_rate()
422 val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); in pll_set_rate()
423 val |= vco->pdiv << ctrl->pdiv.shift; in pll_set_rate()
[all …]
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| D | clk-iproc-armpll.c | 202 unsigned int pdiv; in iproc_arm_pll_recalc_rate() local
218 pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) & in iproc_arm_pll_recalc_rate()
220 if (pdiv == 0) in iproc_arm_pll_recalc_rate()
221 pdiv = 16; in iproc_arm_pll_recalc_rate()
230 pll->rate = (pll->rate / pdiv) / mdiv; in iproc_arm_pll_recalc_rate()
235 (unsigned int)(ndiv >> 20), pdiv, mdiv); in iproc_arm_pll_recalc_rate()
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| D | clk-sr.c | 43 .pdiv = REG_VAL(0x14, 0, 4),
103 .pdiv = REG_VAL(0x14, 0, 4),
162 .pdiv = REG_VAL(0x14, 0, 4),
197 .pdiv = REG_VAL(0x14, 0, 4),
251 .pdiv = REG_VAL(0x14, 0, 4),
287 .pdiv = REG_VAL(0x4, 26, 4),
332 .pdiv = REG_VAL(0x4, 26, 4),
371 .pdiv = REG_VAL(0x4, 26, 4),
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| D | clk-ns2.c | 47 .pdiv = REG_VAL(0x8, 0, 4),
110 .pdiv = REG_VAL(0x8, 0, 4),
172 .pdiv = REG_VAL(0x8, 0, 4),
234 .pdiv = REG_VAL(0x8, 0, 4),
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| D | clk-cygnus.c | 66 .pdiv = REG_VAL(0x14, 0, 4),
124 .pdiv = REG_VAL(0x4, 26, 4),
202 .pdiv = REG_VAL(0x14, 0, 4),
281 .pdiv = REG_VAL(0x44, 0, 4),
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| D | clk-iproc.h | 98 unsigned int pdiv; member
174 struct iproc_clk_reg_op pdiv; member
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| D | clk-nsp.c | 52 .pdiv = REG_VAL(0x18, 24, 3),
109 .pdiv = REG_VAL(0x4, 28, 3),
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| /drivers/clk/imx/ |
| D | clk-pll14xx.c | 77 u32 mdiv, pdiv, sdiv, pll_div; in clk_pll1416x_recalc_rate() local
82 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT; in clk_pll1416x_recalc_rate()
86 do_div(fvco, pdiv << sdiv); in clk_pll1416x_recalc_rate()
95 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; in clk_pll1443x_recalc_rate() local
102 pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT; in clk_pll1443x_recalc_rate()
108 pdiv *= 65536; in clk_pll1443x_recalc_rate()
110 do_div(fvco, pdiv << sdiv); in clk_pll1443x_recalc_rate()
123 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; in clk_pll14xx_mp_change()
172 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
237 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.c | 1217 u32 pdiv; member
1241 params->pdiv = 0; in skl_wrpll_params_populate()
1244 params->pdiv = 1; in skl_wrpll_params_populate()
1247 params->pdiv = 2; in skl_wrpll_params_populate()
1250 params->pdiv = 4; in skl_wrpll_params_populate()
1385 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | in skl_ddi_hdmi_pll_dividers()
2170 static void cnl_wrpll_get_multipliers(int bestdiv, int *pdiv, in cnl_wrpll_get_multipliers() argument
2176 *pdiv = 2; in cnl_wrpll_get_multipliers()
2180 *pdiv = 2; in cnl_wrpll_get_multipliers()
2184 *pdiv = 3; in cnl_wrpll_get_multipliers()
[all …]
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| /drivers/thermal/tegra/ |
| D | tegra132-soctherm.c | 51 .pdiv = 8,
70 .pdiv = 8,
89 .pdiv = 8,
106 .pdiv = 8,
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| D | tegra124-soctherm.c | 51 .pdiv = 8,
70 .pdiv = 8,
89 .pdiv = 8,
106 .pdiv = 8,
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| D | tegra210-soctherm.c | 52 .pdiv = 8,
71 .pdiv = 8,
90 .pdiv = 8,
107 .pdiv = 8,
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| D | soctherm.h | 77 u32 pdiv, pdiv_ate, pdiv_mask; member
89 u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate; member
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| /drivers/clk/st/ |
| D | clk-flexgen.c | 32 struct clk_divider pdiv; member
135 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_recalc_rate()
151 struct clk_hw *pdiv_hw = &flexgen->pdiv.hw; in flexgen_set_rate()
236 fgxbar->pdiv.lock = lock; in clk_register_flexgen()
237 fgxbar->pdiv.reg = reg + 0x58 + idx * 4; in clk_register_flexgen()
238 fgxbar->pdiv.width = 10; in clk_register_flexgen()
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