Searched refs:phyclk_khz (Results 1 – 9 of 9) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 160 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks()
165 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in rv1_update_clocks()
166 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in rv1_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| D | dcn20_clk_mgr.c | 222 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in dcn2_update_clocks()
223 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn2_update_clocks()
225 …pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PHYCLK, clk_mgr_base->clks.phyclk_khz / 100… in dcn2_update_clocks()
329 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) { in dcn2_update_clocks_fpga()
330 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn2_update_clocks_fpga()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| D | dce120_clk_mgr.c | 112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
115 clk_mgr_base->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 78 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) { in rn_update_clocks()
79 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in rn_update_clocks()
80 rn_vbios_smu_set_phyclk(clk_mgr, clk_mgr_base->clks.phyclk_khz); in rn_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clk_mgr.c | 777 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr->clks.phyclk_khz)) { in dce12_update_clocks()
780 clk_mgr->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc.h | 264 int phyclk_khz; member
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 1149 context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level]; in dcn_validate_bandwidth()
1390 dc, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, clocks->phyclk_khz); in dcn_find_dcfclk_suits_all()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hw_sequencer.c | 2696 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0; in dcn10_prepare_bandwidth()
2728 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0; in dcn10_optimize_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc.c | 2488 info->phyClock = (unsigned int)state->bw_ctx.bw.dcn.clk.phyclk_khz; in get_clock_requirements_for_state()
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