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Searched refs:pin_mask (Results 1 – 11 of 11) sorted by relevance

/drivers/gpio/
Dgpio-mxs.c73 u32 pin_mask = 1 << d->hwirq; in mxs_gpio_set_irq_type() local
84 port->both_edges &= ~pin_mask; in mxs_gpio_set_irq_type()
87 val = readl(port->base + PINCTRL_DIN(port)) & pin_mask; in mxs_gpio_set_irq_type()
92 port->both_edges |= pin_mask; in mxs_gpio_set_irq_type()
113 writel(pin_mask, pin_addr + MXS_SET); in mxs_gpio_set_irq_type()
114 writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET); in mxs_gpio_set_irq_type()
116 writel(pin_mask, pin_addr + MXS_CLR); in mxs_gpio_set_irq_type()
117 writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET); in mxs_gpio_set_irq_type()
123 writel(pin_mask, pin_addr + MXS_SET); in mxs_gpio_set_irq_type()
125 writel(pin_mask, pin_addr + MXS_CLR); in mxs_gpio_set_irq_type()
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Dgpio-tegra.c209 u32 pin_mask = BIT(GPIO_BIT(offset)); in tegra_gpio_get_direction() local
213 if (!(cnf & pin_mask)) in tegra_gpio_get_direction()
218 return !(oe & pin_mask); in tegra_gpio_get_direction()
/drivers/soc/fsl/qe/
Dqe_io.c127 u32 pin_mask, tmp_val; in par_io_data_set() local
134 pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); in par_io_data_set()
139 out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val); in par_io_data_set()
141 out_be32(&par_io[port].cpdata, pin_mask | tmp_val); in par_io_data_set()
Dgpio.c57 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_get() local
59 return !!(in_be32(&regs->cpdata) & pin_mask); in qe_gpio_get()
68 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); in qe_gpio_set() local
73 qe_gc->cpdata |= pin_mask; in qe_gpio_set()
75 qe_gc->cpdata &= ~pin_mask; in qe_gpio_set()
/drivers/gpu/drm/i915/
Di915_irq.c1536 u32 *pin_mask, u32 *long_mask, in intel_get_hpd_pins() argument
1543 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); in intel_get_hpd_pins()
1549 *pin_mask |= BIT(pin); in intel_get_hpd_pins()
1556 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); in intel_get_hpd_pins()
1910 u32 pin_mask = 0, long_mask = 0; in i9xx_hpd_irq_handler() local
1917 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in i9xx_hpd_irq_handler()
1922 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
1931 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, in i9xx_hpd_irq_handler()
1935 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); in i9xx_hpd_irq_handler()
2109 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; in ibx_hpd_irq_handler() local
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/drivers/gpu/drm/nouveau/dispnv04/
Dtvnv17.c130 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) in get_tv_detect_quirks() argument
136 *pin_mask = device->quirk->tv_pin_mask; in get_tv_detect_quirks()
151 bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); in nv17_tv_detect()
159 tv_enc->pin_mask = in nv17_tv_detect()
162 tv_enc->pin_mask = in nv17_tv_detect()
166 switch (tv_enc->pin_mask) { in nv17_tv_detect()
807 tv_enc->pin_mask = 0; in nv17_tv_create()
Dtvnv17.h83 uint32_t pin_mask; member
Dtvmodesnv17.c487 if (tv_enc->pin_mask & 0x4) in nv17_tv_update_properties()
489 else if (tv_enc->pin_mask & 0x2) in nv17_tv_update_properties()
/drivers/gpu/drm/i915/display/
Dintel_hotplug.c450 u32 pin_mask, u32 long_mask) in intel_hpd_irq_handler() argument
459 if (!pin_mask) in intel_hpd_irq_handler()
476 if (!(BIT(pin) & pin_mask)) in intel_hpd_irq_handler()
501 if (!(BIT(pin) & pin_mask)) in intel_hpd_irq_handler()
Dintel_hotplug.h22 u32 pin_mask, u32 long_mask);
/drivers/pinctrl/
Dpinctrl-st.c1092 u32 pin_mask = pc->rt_pin_mask; in st_pctl_dt_setup_retime_dedicated() local
1095 if (BIT(j) & pin_mask) { in st_pctl_dt_setup_retime_dedicated()