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Searched refs:pipe_bpp (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dp_mst.c61 crtc_state->pipe_bpp = bpp; in intel_dp_mst_compute_link_config()
64 crtc_state->pipe_bpp); in intel_dp_mst_compute_link_config()
79 intel_link_compute_m_n(crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
139 limits.max_bpp = min(pipe_config->pipe_bpp, 24); in intel_dp_mst_compute_config()
Dintel_lvds.c291 if (pipe_config->dither && pipe_config->pipe_bpp == 18) in intel_pre_enable_lvds()
410 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
412 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
413 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
Dintel_hdmi.c913 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
918 switch (pipe_bpp) { in gcp_default_phase_possible()
1008 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1012 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
1738 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
1908 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
1954 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
1966 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
2209 if (crtc_state->pipe_bpp < bpc * 3) in hdmi_deep_color_possible()
2387 pipe_config->pipe_bpp = desired_bpp; in intel_hdmi_compute_config()
Dintel_dp.c1874 bpp = pipe_config->pipe_bpp; in intel_dp_compute_bpp()
1968 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
2004 int pipe_bpp; in intel_dp_dsc_compute_config() local
2016 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); in intel_dp_dsc_compute_config()
2017 if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) { in intel_dp_dsc_compute_config()
2027 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_config()
2034 pipe_config->pipe_bpp); in intel_dp_dsc_compute_config()
2057 pipe_config->pipe_bpp); in intel_dp_dsc_compute_config()
2078 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
2086 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
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Dintel_ddi.c1470 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) in ddi_dotclock_get()
1471 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; in ddi_dotclock_get()
1712 switch (crtc_state->pipe_bpp) { in intel_ddi_set_pipe_settings()
1726 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_pipe_settings()
1781 switch (crtc_state->pipe_bpp) { in intel_ddi_enable_transcoder_func()
3849 pipe_config->pipe_bpp = 18; in intel_ddi_get_config()
3852 pipe_config->pipe_bpp = 24; in intel_ddi_get_config()
3855 pipe_config->pipe_bpp = 30; in intel_ddi_get_config()
3858 pipe_config->pipe_bpp = 36; in intel_ddi_get_config()
3909 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_ddi_get_config()
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Dintel_crt.c408 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
413 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
Dintel_audio.c263 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
266 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
Dintel_display.c7275 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
7279 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ironlake_fdi_compute_config()
7286 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ironlake_fdi_compute_config()
7287 pipe_config->pipe_bpp -= 2*3; in ironlake_fdi_compute_config()
7289 pipe_config->pipe_bpp); in ironlake_fdi_compute_config()
7314 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
8298 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
8302 switch (crtc_state->pipe_bpp) { in i9xx_set_pipeconf()
8794 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
8797 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
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Dvlv_dsi.c290 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
292 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1063 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in bxt_dsi_get_pipe_config()
Dintel_vdsc.c382 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dp_compute_dsc_params()
Dintel_display_types.h859 int pipe_bpp; member
Dicl_dsi.c1258 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in gen11_dsi_get_config()
Dintel_tv.c1205 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
Dintel_panel.c443 if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18) in intel_gmch_panel_fitting()
Dintel_sdvo.c1283 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()
/drivers/gpu/drm/i915/
Di915_debugfs.c2740 yesno(pipe_config->dither), pipe_config->pipe_bpp); in i915_display_info()