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Searched refs:pixel_table (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/powerplay/inc/
Dsmu_v11_0.h99 struct smu_11_0_dpm_table pixel_table; member
/drivers/gpu/drm/amd/powerplay/
Dvega20_ppt.h117 struct vega20_single_dpm_table pixel_table; member
Dnavi10_ppt.c612 dpm_context->dpm_tables.pixel_table.min = driver_ppt->FreqTablePixclk[0]; in navi10_set_default_dpm_table()
613 dpm_context->dpm_tables.pixel_table.max = driver_ppt->FreqTablePixclk[NUM_PIXCLK_DPM_LEVELS - 1]; in navi10_set_default_dpm_table()
Dvega20_ppt.c831 single_dpm_table = &(dpm_table->pixel_table); in vega20_set_default_dpm_table()
/drivers/clk/qcom/
Dclk-rcg.c586 static const struct frac_entry pixel_table[] = { variable
597 const struct frac_entry *frac = pixel_table; in clk_rcg_pixel_determine_rate()
622 const struct frac_entry *frac = pixel_table; in clk_rcg_pixel_set_rate()
/drivers/gpu/drm/amd/powerplay/hwmgr/
Dvega10_hwmgr.h154 struct vega10_single_dpm_table pixel_table; member
Dvega12_hwmgr.h133 struct vega12_single_dpm_table pixel_table; member
Dvega20_hwmgr.h185 struct vega20_single_dpm_table pixel_table; member
Dvega12_hwmgr.c653 dpm_table = &(data->dpm_table.pixel_table); in vega12_setup_default_dpm_tables()
Dvega20_hwmgr.c723 dpm_table = &(data->dpm_table.pixel_table); in vega20_setup_default_dpm_tables()
Dvega10_hwmgr.c1417 dpm_table = &(data->dpm_table.pixel_table); in vega10_setup_default_dpm_tables()