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Searched refs:port_cap (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/
Ddrm_dp_helper.c478 const u8 port_cap[4]) in drm_dp_downstream_max_clock()
480 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; in drm_dp_downstream_max_clock()
489 return port_cap[1] * 8 * 1000; in drm_dp_downstream_max_clock()
493 return port_cap[1] * 2500; in drm_dp_downstream_max_clock()
509 const u8 port_cap[4]) in drm_dp_downstream_max_bpc()
511 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; in drm_dp_downstream_max_bpc()
524 bpc = port_cap[2] & DP_DS_MAX_BPC_MASK; in drm_dp_downstream_max_bpc()
566 const u8 port_cap[4], struct drm_dp_aux *aux) in drm_dp_downstream_debug()
575 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; in drm_dp_downstream_debug()
625 clk = drm_dp_downstream_max_clock(dpcd, port_cap); in drm_dp_downstream_debug()
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/drivers/net/ethernet/mellanox/mlx4/
Dfw.c1106 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); in mlx4_QUERY_DEV_CAP()
1157 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, in mlx4_dev_cap_dump()
1158 dev_cap->port_cap[1].max_port_width); in mlx4_dev_cap_dump()
1183 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) in mlx4_QUERY_PORT() argument
1205 port_cap->max_vl = field >> 4; in mlx4_QUERY_PORT()
1207 port_cap->ib_mtu = field >> 4; in mlx4_QUERY_PORT()
1208 port_cap->max_port_width = field & 0xf; in mlx4_QUERY_PORT()
1210 port_cap->max_gids = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1212 port_cap->max_pkeys = 1 << (field & 0xf); in mlx4_QUERY_PORT()
1232 port_cap->link_state = (field & 0x80) >> 7; in mlx4_QUERY_PORT()
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Dmain.c398 struct mlx4_port_cap *port_cap) in _mlx4_dev_port() argument
400 dev->caps.vl_cap[port] = port_cap->max_vl; in _mlx4_dev_port()
401 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu; in _mlx4_dev_port()
402 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids; in _mlx4_dev_port()
403 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys; in _mlx4_dev_port()
407 dev->caps.gid_table_len[port] = port_cap->max_gids; in _mlx4_dev_port()
408 dev->caps.pkey_table_len[port] = port_cap->max_pkeys; in _mlx4_dev_port()
409 dev->caps.port_width_cap[port] = port_cap->max_port_width; in _mlx4_dev_port()
410 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu; in _mlx4_dev_port()
411 dev->caps.max_tc_eth = port_cap->max_tc_eth; in _mlx4_dev_port()
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Dfw.h132 struct mlx4_port_cap port_cap[MLX4_MAX_PORTS + 1]; member
231 int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap);
Deq.c157 struct mlx4_port_cap port_cap; in mlx4_gen_slave_eqe() local
159 if (!mlx4_QUERY_PORT(dev, 1, &port_cap) && port_cap.link_state) in mlx4_gen_slave_eqe()
162 if (!mlx4_QUERY_PORT(dev, 2, &port_cap) && port_cap.link_state) in mlx4_gen_slave_eqe()
/drivers/net/ethernet/huawei/hinic/
Dhinic_ethtool.c80 struct hinic_port_cap port_cap; in hinic_get_link_ksettings() local
91 err = hinic_port_get_cap(nic_dev, &port_cap); in hinic_get_link_ksettings()
102 set_link_speed(link_ksettings, port_cap.speed); in hinic_get_link_ksettings()
104 if (!!(port_cap.autoneg_cap & HINIC_AUTONEG_SUPPORTED)) in hinic_get_link_ksettings()
108 if (port_cap.autoneg_state == HINIC_AUTONEG_ACTIVE) in hinic_get_link_ksettings()
111 link_ksettings->base.duplex = (port_cap.duplex == HINIC_DUPLEX_FULL) ? in hinic_get_link_ksettings()
Dhinic_port.c349 struct hinic_port_cap *port_cap) in hinic_port_get_cap() argument
357 port_cap->func_idx = HINIC_HWIF_FUNC_IDX(hwif); in hinic_port_get_cap()
360 port_cap, sizeof(*port_cap), in hinic_port_get_cap()
361 port_cap, &out_size); in hinic_port_get_cap()
362 if (err || (out_size != sizeof(*port_cap)) || port_cap->status) { in hinic_port_get_cap()
365 port_cap->status); in hinic_port_get_cap()
Dhinic_port.h535 struct hinic_port_cap *port_cap);