Home
last modified time | relevance | path

Searched refs:post_fix (Results 1 – 25 of 34) sorted by relevance

12

/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
Dhw_factory_dcn21.c61 #define SF_HPD(reg_name, field_name, post_fix)\ argument
62 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
68 #define SF(reg_name, field_name, post_fix)\ argument
69 .field_name = reg_name ## __ ## field_name ## post_fix
100 #define SF_DDC(reg_name, field_name, post_fix)\ argument
101 .field_name = reg_name ## __ ## field_name ## post_fix
140 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
141 .field_name = reg_name ## __ ## field_name ## post_fix
Dhw_translate_dcn21.c58 #define SF_HPD(reg_name, field_name, post_fix)\ argument
59 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
Dhw_factory_dcn20.c63 #define SF_HPD(reg_name, field_name, post_fix)\ argument
64 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
70 #define SF(reg_name, field_name, post_fix)\ argument
71 .field_name = reg_name ## __ ## field_name ## post_fix
103 #define SF_DDC(reg_name, field_name, post_fix)\ argument
104 .field_name = reg_name ## __ ## field_name ## post_fix
145 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
146 .field_name = reg_name ## __ ## field_name ## post_fix
Dhw_translate_dcn20.c58 #define SF_HPD(reg_name, field_name, post_fix)\ argument
59 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dce120/
Dhw_factory_dce120.c46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
97 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
Dhw_factory_dcn10.c47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
48 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
93 .field_name = reg_name ## __ ## field_name ## post_fix
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
129 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dce110/
Dhw_factory_dce110.c42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = reg_name ## __ ## field_name ## post_fix
83 #define SF_DDC(reg_name, field_name, post_fix)\ argument
84 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dccg.h44 #define DCCG_SF(reg_name, field_name, post_fix)\ argument
45 .field_name = reg_name ## __ ## field_name ## post_fix
47 #define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\ argument
48 …ix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
Ddcn20_vmid.h41 #define SF(reg_name, field_name, post_fix)\ argument
42 .field_name = reg_name ## __ ## field_name ## post_fix
Ddcn20_opp.h33 #define OPP_SF(reg_name, field_name, post_fix)\ argument
34 .field_name = reg_name ## __ ## field_name ## post_fix
Ddcn20_dsc.h88 #define DSC_SF(reg_name, field_name, post_fix)\ argument
89 .field_name = reg_name ## __ ## field_name ## post_fix
92 #define DSC2_SF(reg_name, field_name, post_fix)\ argument
93 .field_name = reg_name ## _ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/gpio/dce80/
Dhw_factory_dce80.c83 #define SF_DDC(reg_name, field_name, post_fix)\ argument
84 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_audio.h44 #define SF(reg_name, field_name, post_fix)\ argument
45 .field_name = reg_name ## __ ## field_name ## post_fix
Ddce_dmcu.h74 #define DMCU_SF(reg_name, field_name, post_fix)\ argument
75 .field_name = reg_name ## __ ## field_name ## post_fix
Ddce_clock_source.h45 #define CS_SF(reg_name, field_name, post_fix)\ argument
46 .field_name = reg_name ## __ ## field_name ## post_fix
Ddce_abm.h86 #define ABM_SF(reg_name, field_name, post_fix)\ argument
87 .field_name = reg_name ## __ ## field_name ## post_fix
Ddce_ipp.h64 #define IPP_SF(reg_name, field_name, post_fix)\ argument
65 .field_name = reg_name ## __ ## field_name ## post_fix
Ddce_i2c_hw.h98 #define I2C_SF(reg_name, field_name, post_fix)\ argument
99 .field_name = reg_name ## __ ## field_name ## post_fix
Ddce_opp.h84 #define OPP_SF(reg_name, field_name, post_fix)\ argument
85 .field_name = reg_name ## __ ## field_name ## post_fix
Ddce_hwseq.h442 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ argument
443 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix
445 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ argument
446 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr_internal.h106 #define CLK_SF(reg_name, field_name, post_fix)\ argument
107 .field_name = reg_name ## __ ## field_name ## post_fix
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_opp.h33 #define OPP_SF(reg_name, field_name, post_fix)\ argument
34 .field_name = reg_name ## __ ## field_name ## post_fix
Ddcn10_ipp.h74 #define IPP_SF(reg_name, field_name, post_fix)\ argument
75 .field_name = reg_name ## __ ## field_name ## post_fix
Ddcn10_hubbub.h147 #define HUBBUB_SF(reg_name, field_name, post_fix)\ argument
148 .field_name = reg_name ## __ ## field_name ## post_fix
Ddcn10_dwb.h49 #define SF(reg_name, field_name, post_fix)\ argument
50 .field_name = reg_name ## __ ## field_name ## post_fix

12