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Searched refs:preg (Results 1 – 9 of 9) sorted by relevance

/drivers/video/fbdev/
Dcontrolfb.h35 struct preg { /* padded register */ struct
41 struct preg vcount; /* vertical counter */ argument
43 struct preg vswin; /* between vsblank and vssync */
44 struct preg vsblank; /* vert start blank */
45 struct preg veblank; /* vert end blank (display start) */
46 struct preg vewin; /* between vesync and veblank */
47 struct preg vesync; /* vert end sync */
48 struct preg vssync; /* vert start sync */
49 struct preg vperiod; /* vert period */
50 struct preg piped; /* pipe delay hardware cursor */
[all …]
Dplatinumfb.h39 struct preg { /* padded register */ struct
45 struct preg reg[128]; argument
Dcontrolfb.c479 volatile struct preg __iomem *rp; in control_set_hardware()
/drivers/leds/
Dleds-lm355x.c201 struct lm355x_reg_data *preg = chip->regs; in lm355x_control() local
203 ret = regmap_read(chip->regmap, preg[REG_FLAG].regno, &chip->last_flag); in lm355x_control()
206 if (chip->last_flag & preg[REG_FLAG].mask) in lm355x_control()
209 chip->last_flag & preg[REG_FLAG].mask); in lm355x_control()
217 regmap_update_bits(chip->regmap, preg[REG_TORCH_CTRL].regno, in lm355x_control()
218 preg[REG_TORCH_CTRL].mask, in lm355x_control()
220 << preg[REG_TORCH_CTRL].shift); in lm355x_control()
227 preg[REG_TORCH_CFG].regno, in lm355x_control()
228 preg[REG_TORCH_CFG].mask, in lm355x_control()
230 preg[REG_TORCH_CFG].shift); in lm355x_control()
[all …]
/drivers/macintosh/
Dmacio-adb.c21 struct preg { struct
27 struct preg intr; argument
28 struct preg data[9];
29 struct preg intr_enb;
30 struct preg dcount;
31 struct preg error;
32 struct preg ctrl;
33 struct preg autopoll;
34 struct preg active_hi;
35 struct preg active_lo;
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/drivers/staging/emxx_udc/
Demxx_udc.c375 struct fc_regs __iomem *preg = udc->p_regs; in _nbu2ss_ep_dma_exit() local
380 data = _nbu2ss_readl(&preg->USBSSCONF); in _nbu2ss_ep_dma_exit()
391 _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0); in _nbu2ss_ep_dma_exit()
392 _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_DIR0); in _nbu2ss_ep_dma_exit()
393 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); in _nbu2ss_ep_dma_exit()
397 _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); in _nbu2ss_ep_dma_exit()
398 _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); in _nbu2ss_ep_dma_exit()
406 struct fc_regs __iomem *preg = udc->p_regs; in _nbu2ss_ep_dma_abort() local
408 _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPN_REQEN); in _nbu2ss_ep_dma_abort()
410 _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPN_DMA_EN); in _nbu2ss_ep_dma_abort()
[all …]
/drivers/gpu/drm/i915/gvt/
Ddebugfs.c38 u32 preg; member
64 u32 preg, vreg; in mmio_diff_handler() local
66 preg = intel_uncore_read_notrace(&i915->uncore, _MMIO(offset)); in mmio_diff_handler()
69 if (preg != vreg) { in mmio_diff_handler()
75 node->preg = preg; in mmio_diff_handler()
114 u32 diff = node->preg ^ node->vreg; in vgpu_mmio_diff_show()
117 node->offset, node->preg, node->vreg, in vgpu_mmio_diff_show()
/drivers/crypto/stm32/
Dstm32-hash.c959 u32 *preg; in stm32_hash_export() local
971 preg = rctx->hw_context; in stm32_hash_export()
973 *preg++ = stm32_hash_read(hdev, HASH_IMR); in stm32_hash_export()
974 *preg++ = stm32_hash_read(hdev, HASH_STR); in stm32_hash_export()
975 *preg++ = stm32_hash_read(hdev, HASH_CR); in stm32_hash_export()
977 *preg++ = stm32_hash_read(hdev, HASH_CSR(i)); in stm32_hash_export()
992 const u32 *preg = in; in stm32_hash_import() local
998 preg = rctx->hw_context; in stm32_hash_import()
1002 stm32_hash_write(hdev, HASH_IMR, *preg++); in stm32_hash_import()
1003 stm32_hash_write(hdev, HASH_STR, *preg++); in stm32_hash_import()
[all …]
/drivers/gpu/drm/msm/hdmi/
Dhdmi_hdcp.c156 static int msm_hdmi_hdcp_scm_wr(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 *preg, in msm_hdmi_hdcp_scm_wr() argument
164 WARN_ON(!pdata || !preg || (count == 0)); in msm_hdmi_hdcp_scm_wr()
173 scm_buf[i].addr = phy_addr + preg[idx]; in msm_hdmi_hdcp_scm_wr()
190 hdmi_write(hdmi, preg[i], pdata[i]); in msm_hdmi_hdcp_scm_wr()