Home
last modified time | relevance | path

Searched refs:r0 (Results 1 – 25 of 54) sorted by relevance

123

/drivers/memory/
Dti-emif-sram-pm.S53 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
57 ldr r1, [r0, #EMIF_SDRAM_CONFIG]
60 ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
63 ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
66 ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
69 ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
72 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
75 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
78 ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
81 ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
[all …]
/drivers/soc/bcm/brcmstb/pm/
Ds2-arm.S23 mov AON_CTRL_REG, r0
30 ldr r0, [DDR_PHY_STATUS_REG]
33 ldr r0, =PM_S2_COMMAND
37 str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
38 ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
45 1: ldr r0, [DDR_PHY_STATUS_REG]
46 ands r0, #1
50 ldr r0, =1
51 str r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
52 ldr r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
Dmacros.fuc194 */ mov $r0 ior /*
195 */ shl b32 $r0 6 /*
196 */ iowr I[$r0 + 0x000] reg /*
197 */ clear b32 $r0
200 */ mov $r0 ior /*
201 */ iowr I[$r0 + 0x000] reg /*
202 */ clear b32 $r0
207 */ mov $r0 ior /*
208 */ shl b32 $r0 6 /*
209 */ iowrs I[$r0 + 0x000] reg /*
[all …]
Dkernel.fuc51 // $r0 - zero
68 // $r0 - zero
96 // $r0 - zero
117 // $r0 - zero
147 ld b32 $r10 D[$r0 + #time_prev]
159 ld b32 $r10 D[$r0 + #time_next]
166 st b32 D[$r0 + #time_next] $r9
177 push $r0
178 clear b32 $r0
198 st b32 D[$r0 + #time_next] $r0
[all …]
Dmemx.fuc82 // $r0 - zero
118 st b32 D[$r0 + #memx_ts_start] $r6
126 // $r0 - zero
129 st b32 D[$r0 + #memx_ts_end] $r6
170 // $r0 - zero
208 // $r0 - zero
222 // $r0 - zero
241 // $r0 - zero
258 // $r0 - zero
270 // $r0 - zero
[all …]
Di2c_.fuc82 // $r0 - zero
205 // $r0 - zero
220 // $r0 - zero
310 // $r0 - zero
390 // $r0 - zero
/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s99 // $r0 is always set to 0 in our code - this allows some space savings.
100 clear b32 $r0
107 mov $sp $r0
136 iord $r1 I[$r0 + 0x200]
145 mov $xdbase $r0
159 xdst $r0 $r2
180 xdld $r0 $r2
262 ld b32 $r7 D[$r0 + #ctx_cond_off]
283 iowr I[$r0] $r4
286 iord $r4 I[$r0 + 0x200]
[all …]
/drivers/scsi/arm/
Dacornscsi-io.S23 bic r0, r0, #3
29 ldmia r0!, {r3, r4, r5, r6}
34 ldmia r0!, {r5, r6, r7, ip}
45 ldmia r0!, {r3, r4, r5, r6}
56 ldmia r0!, {r3, r4}
64 ldr r3, [r0], #4
77 bic r0, r0, #3
90 stmia r0!, {r3, r4, r5, r6}
99 stmia r0!, {r3, r4, ip, lr}
114 stmia r0!, {r3, r4, r5, r6}
[all …]
/drivers/firmware/
Dqcom_scm-32.c122 register u32 r0 asm("r0") = 1; in smc()
135 : "=r" (r0) in smc()
136 : "r" (r0), "r" (r1), "r" (r2) in smc()
138 } while (r0 == QCOM_SCM_INTERRUPTED); in smc()
140 return r0; in smc()
238 register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1); in qcom_scm_call_atomic1()
251 : "=r" (r0) in qcom_scm_call_atomic1()
252 : "r" (r0), "r" (r1), "r" (r2) in qcom_scm_call_atomic1()
254 return r0; in qcom_scm_call_atomic1()
271 register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 2); in qcom_scm_call_atomic2()
[all …]
Dtrusted_foundations.c36 register u32 r0 asm("r0") = type; in tf_generic_smc()
51 : "r" (r0), "r" (r1), "r" (r2) in tf_generic_smc()
/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
Dgpc.fuc125 clear b32 $r0
140 nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0)
155 st b32 D[$r0 + #tpc_count] $r2
156 st b32 D[$r0 + #tpc_mask] $r3
160 st b32 D[$r0 + #gpc_id] $r2
184 st b32 D[$r0 + #unk_count] $r3
185 st b32 D[$r0 + #unk_mask] $r4
199 ld b32 $r14 D[$r0 + #gpc_mmio_list_head]
200 ld b32 $r15 D[$r0 + #gpc_mmio_list_tail]
206 ld b32 $r14 D[$r0 + #tpc_mmio_list_head]
[all …]
Dhub.fuc70 clear b32 $r0
71 mov $xdbase $r0
106 sub b32 $r3 $r0 1
123 st b32 D[$r0 + #rop_count] $r1
125 st b32 D[$r0 + #gpc_count] $r15
145 ld b32 $r14 D[$r0 + #hub_mmio_list_head]
146 ld b32 $r15 D[$r0 + #hub_mmio_list_tail]
175 ld b32 $r3 D[$r0 + #gpc_count]
310 push $r0
320 clear b32 $r0
[all …]
/drivers/gpu/drm/nouveau/nvkm/engine/ce/fuc/
Dcom.fuc137 clear b32 $r0
138 mov $sp $r0
166 iord $r1 I[$r0 + 0x200]
178 iowr I[$r0 + 0x100] $r1
188 mov $xdbase $r0
229 mov b32 $r4 $r0
234 xdst $r0 $r4
237 xdld $r0 $r4
345 iowr I[$r0] $r2
347 iord $r2 I[$r0 + 0x200]
[all …]
/drivers/block/paride/
Dbpck.c64 t2(4); h = r0(); in bpck_read_regr()
167 for(i=0;i<count;i++) { t2(4); buf[i] = r0(); } in bpck_read_block()
205 o0 = r0(); in bpck_probe_unit()
221 { pi->saved_r0 = r0(); in bpck_connect()
264 { pi->saved_r0 = r0(); in bpck_force_spp()
301 for(i=0;i<TEST_LEN;i++) { t2(4); buf[i] = r0(); } in bpck_test_proto()
403 w2(0x2c); i = r0(); w0(255-i); r = r0(); w0(i); in bpck_test_port()
408 w2(0xc); i = r0(); w0(255-i); r = r0(); w0(i); in bpck_test_port()
411 if (m == 0) { w2(6); w2(0xc); r = r0(); w0(0xaa); w0(r); w0(0xaa); } in bpck_test_port()
Daten.c63 a = r0(); in aten_read_regr()
90 a = r0(); w2(0x20); b = r0(); in aten_read_block()
112 { pi->saved_r0 = r0(); in aten_connect()
Dfit3.c80 w2(0xec); w2(0xee); w2(0xef); a = r0(); in fit3_read_regr()
116 w2(0xef); a = r0(); in fit3_read_block()
117 w2(0xee); b = r0(); in fit3_read_block()
157 { pi->saved_r0 = r0(); in fit3_connect()
Dkbic.c62 a = r0(); w2(4); in kbic_read_regr()
101 { pi->saved_r0 = r0(); in k951_connect()
117 { pi->saved_r0 = r0(); in k971_connect()
167 w2(0xa0); w2(0xa1); buf[2*k] = r0(); in kbic_read_block()
168 w2(0xa5); buf[2*k+1] = r0(); in kbic_read_block()
Don26.c62 w2(0x26); a = r0(); w2(4); w2(0x26); w2(4); in on26_read_regr()
106 pi->saved_r0 = r0(); in on26_connect()
131 pi->saved_r0 = r0(); in on26_test_port()
205 w2(0x26); buf[2*k] = r0(); in on26_read_block()
206 w2(0x24); buf[2*k+1] = r0(); in on26_read_block()
Don20.c51 case 1: w2(4); w2(0x26); r = r0(); in on20_read_regr()
72 { pi->saved_r0 = r0(); in on20_connect()
95 w2(4); w2(0x26); buf[k] = r0(); in on20_read_block()
Dcomm.c58 w0(0); w2(0x26); h = r0(); w2(4); in comm_read_regr()
92 { pi->saved_r0 = r0(); in comm_connect()
124 w2(0x26); buf[i] = r0(); w2(0x24); in comm_read_block()
Ddstr.c62 case 1: w0(0); w2(0x26); a = r0(); w2(4); in dstr_read_regr()
103 { pi->saved_r0 = r0(); in dstr_connect()
134 w2(0x26); buf[k] = r0(); w2(0x24); in dstr_read_block()
Depat.c85 a = r0(); w2(4); in epat_read_regr()
132 buf[k] = r0(); in epat_read_block()
135 w2(0x26); w2(0x27); buf[count-1] = r0(); in epat_read_block()
215 { pi->saved_r0 = r0(); in epat_connect()
/drivers/net/wireless/atmel/
Datmel.c4320 mov r0, #CPSR_INITIAL
4321 msr CPSR_c, r0 /* This is probably unnecessary */
4324 ldr r0, =SPI_CGEN_BASE
4328 str r1, [r0]
4329 ldr r1, [r0, #28]
4331 str r1, [r0, #28]
4333 str r1, [r0, #8]
4335 ldr r0, =MRBASE
4337 strh r1, [r0, #MR1]
4338 strh r1, [r0, #MR2]
[all …]
/drivers/media/tuners/
Dtda18271-maps.c896 u8 r0; member
901 { .d = 0x00, .r0 = 60, .r1 = 92 },
902 { .d = 0x01, .r0 = 62, .r1 = 94 },
903 { .d = 0x02, .r0 = 66, .r1 = 98 },
904 { .d = 0x03, .r0 = 64, .r1 = 96 },
905 { .d = 0x04, .r0 = 74, .r1 = 106 },
906 { .d = 0x05, .r0 = 72, .r1 = 104 },
907 { .d = 0x06, .r0 = 68, .r1 = 100 },
908 { .d = 0x07, .r0 = 70, .r1 = 102 },
909 { .d = 0x08, .r0 = 90, .r1 = 122 },
[all …]
/drivers/mtd/nand/raw/
Dtmio_nand.c292 int r0, r1; in tmio_nand_correct_data() local
295 r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256, false); in tmio_nand_correct_data()
296 if (r0 < 0) in tmio_nand_correct_data()
297 return r0; in tmio_nand_correct_data()
302 return r0 + r1; in tmio_nand_correct_data()

123