1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 Madge Ambassador ATM Adapter driver. 4 Copyright (C) 1995-1999 Madge Networks Ltd. 5 6 */ 7 8 #ifndef AMBASSADOR_H 9 #define AMBASSADOR_H 10 11 12 #ifdef CONFIG_ATM_AMBASSADOR_DEBUG 13 #define DEBUG_AMBASSADOR 14 #endif 15 16 #define DEV_LABEL "amb" 17 18 #ifndef PCI_VENDOR_ID_MADGE 19 #define PCI_VENDOR_ID_MADGE 0x10B6 20 #endif 21 #ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR 22 #define PCI_DEVICE_ID_MADGE_AMBASSADOR 0x1001 23 #endif 24 #ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR_BAD 25 #define PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD 0x1002 26 #endif 27 28 // diagnostic output 29 30 #define PRINTK(severity,format,args...) \ 31 printk(severity DEV_LABEL ": " format "\n" , ## args) 32 33 #ifdef DEBUG_AMBASSADOR 34 35 #define DBG_ERR 0x0001 36 #define DBG_WARN 0x0002 37 #define DBG_INFO 0x0004 38 #define DBG_INIT 0x0008 39 #define DBG_LOAD 0x0010 40 #define DBG_VCC 0x0020 41 #define DBG_QOS 0x0040 42 #define DBG_CMD 0x0080 43 #define DBG_TX 0x0100 44 #define DBG_RX 0x0200 45 #define DBG_SKB 0x0400 46 #define DBG_POOL 0x0800 47 #define DBG_IRQ 0x1000 48 #define DBG_FLOW 0x2000 49 #define DBG_REGS 0x4000 50 #define DBG_DATA 0x8000 51 #define DBG_MASK 0xffff 52 53 /* the ## prevents the annoying double expansion of the macro arguments */ 54 /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */ 55 #define PRINTDB(bits,format,args...) \ 56 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 ) 57 #define PRINTDM(bits,format,args...) \ 58 ( (debug & (bits)) ? printk (format , ## args) : 1 ) 59 #define PRINTDE(bits,format,args...) \ 60 ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 ) 61 #define PRINTD(bits,format,args...) \ 62 ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 ) 63 64 #else 65 66 #define PRINTD(bits,format,args...) 67 #define PRINTDB(bits,format,args...) 68 #define PRINTDM(bits,format,args...) 69 #define PRINTDE(bits,format,args...) 70 71 #endif 72 73 #define PRINTDD(bits,format,args...) 74 #define PRINTDDB(sec,fmt,args...) 75 #define PRINTDDM(sec,fmt,args...) 76 #define PRINTDDE(sec,fmt,args...) 77 78 // tunable values (?) 79 80 /* MUST be powers of two -- why ? */ 81 #define COM_Q_ENTRIES 8 82 #define TX_Q_ENTRIES 32 83 #define RX_Q_ENTRIES 64 84 85 // fixed values 86 87 // guessing 88 #define AMB_EXTENT 0x80 89 90 // Minimum allowed size for an Ambassador queue 91 #define MIN_QUEUE_SIZE 2 92 93 // Ambassador microcode allows 1 to 4 pools, we use 4 (simpler) 94 #define NUM_RX_POOLS 4 95 96 // minimum RX buffers required to cope with replenishing delay 97 #define MIN_RX_BUFFERS 1 98 99 // minimum PCI latency we will tolerate (32 IS TOO SMALL) 100 #define MIN_PCI_LATENCY 64 // 255 101 102 // VCs supported by card (VPI always 0) 103 #define NUM_VPI_BITS 0 104 #define NUM_VCI_BITS 10 105 #define NUM_VCS 1024 106 107 /* The status field bits defined so far. */ 108 #define RX_ERR 0x8000 // always present if there is an error (hmm) 109 #define CRC_ERR 0x4000 // AAL5 CRC error 110 #define LEN_ERR 0x2000 // overlength frame 111 #define ABORT_ERR 0x1000 // zero length field in received frame 112 #define UNUSED_ERR 0x0800 // buffer returned unused 113 114 // Adaptor commands 115 116 #define SRB_OPEN_VC 0 117 /* par_0: dwordswap(VC_number) */ 118 /* par_1: dwordswap(flags<<16) or wordswap(flags)*/ 119 /* flags: */ 120 121 /* LANE: 0x0004 */ 122 /* NOT_UBR: 0x0008 */ 123 /* ABR: 0x0010 */ 124 125 /* RxPool0: 0x0000 */ 126 /* RxPool1: 0x0020 */ 127 /* RxPool2: 0x0040 */ 128 /* RxPool3: 0x0060 */ 129 130 /* par_2: dwordswap(fp_rate<<16) or wordswap(fp_rate) */ 131 132 #define SRB_CLOSE_VC 1 133 /* par_0: dwordswap(VC_number) */ 134 135 #define SRB_GET_BIA 2 136 /* returns */ 137 /* par_0: dwordswap(half BIA) */ 138 /* par_1: dwordswap(half BIA) */ 139 140 #define SRB_GET_SUNI_STATS 3 141 /* par_0: dwordswap(physical_host_address) */ 142 143 #define SRB_SET_BITS_8 4 144 #define SRB_SET_BITS_16 5 145 #define SRB_SET_BITS_32 6 146 #define SRB_CLEAR_BITS_8 7 147 #define SRB_CLEAR_BITS_16 8 148 #define SRB_CLEAR_BITS_32 9 149 /* par_0: dwordswap(ATMizer address) */ 150 /* par_1: dwordswap(mask) */ 151 152 #define SRB_SET_8 10 153 #define SRB_SET_16 11 154 #define SRB_SET_32 12 155 /* par_0: dwordswap(ATMizer address) */ 156 /* par_1: dwordswap(data) */ 157 158 #define SRB_GET_32 13 159 /* par_0: dwordswap(ATMizer address) */ 160 /* returns */ 161 /* par_1: dwordswap(ATMizer data) */ 162 163 #define SRB_GET_VERSION 14 164 /* returns */ 165 /* par_0: dwordswap(Major Version) */ 166 /* par_1: dwordswap(Minor Version) */ 167 168 #define SRB_FLUSH_BUFFER_Q 15 169 /* Only flags to define which buffer pool; all others must be zero */ 170 /* par_0: dwordswap(flags<<16) or wordswap(flags)*/ 171 172 #define SRB_GET_DMA_SPEEDS 16 173 /* returns */ 174 /* par_0: dwordswap(Read speed (bytes/sec)) */ 175 /* par_1: dwordswap(Write speed (bytes/sec)) */ 176 177 #define SRB_MODIFY_VC_RATE 17 178 /* par_0: dwordswap(VC_number) */ 179 /* par_1: dwordswap(fp_rate<<16) or wordswap(fp_rate) */ 180 181 #define SRB_MODIFY_VC_FLAGS 18 182 /* par_0: dwordswap(VC_number) */ 183 /* par_1: dwordswap(flags<<16) or wordswap(flags)*/ 184 185 /* flags: */ 186 187 /* LANE: 0x0004 */ 188 /* NOT_UBR: 0x0008 */ 189 /* ABR: 0x0010 */ 190 191 /* RxPool0: 0x0000 */ 192 /* RxPool1: 0x0020 */ 193 /* RxPool2: 0x0040 */ 194 /* RxPool3: 0x0060 */ 195 196 #define SRB_RATE_SHIFT 16 197 #define SRB_POOL_SHIFT (SRB_FLAGS_SHIFT+5) 198 #define SRB_FLAGS_SHIFT 16 199 200 #define SRB_STOP_TASKING 19 201 #define SRB_START_TASKING 20 202 #define SRB_SHUT_DOWN 21 203 #define MAX_SRB 21 204 205 #define SRB_COMPLETE 0xffffffff 206 207 #define TX_FRAME 0x80000000 208 209 // number of types of SRB MUST be a power of two -- why? 210 #define NUM_OF_SRB 32 211 212 // number of bits of period info for rate 213 #define MAX_RATE_BITS 6 214 215 #define TX_UBR 0x0000 216 #define TX_UBR_CAPPED 0x0008 217 #define TX_ABR 0x0018 218 #define TX_FRAME_NOTCAP 0x0000 219 #define TX_FRAME_CAPPED 0x8000 220 221 #define FP_155_RATE 0x24b1 222 #define FP_25_RATE 0x1f9d 223 224 /* #define VERSION_NUMBER 0x01000000 // initial release */ 225 /* #define VERSION_NUMBER 0x01010000 // fixed startup probs PLX MB0 not cleared */ 226 /* #define VERSION_NUMBER 0x01020000 // changed SUNI reset timings; allowed r/w onchip */ 227 228 /* #define VERSION_NUMBER 0x01030000 // clear local doorbell int reg on reset */ 229 /* #define VERSION_NUMBER 0x01040000 // PLX bug work around version PLUS */ 230 /* remove race conditions on basic interface */ 231 /* indicate to the host that diagnostics */ 232 /* have finished; if failed, how and what */ 233 /* failed */ 234 /* fix host memory test to fix PLX bug */ 235 /* allow flash upgrade and BIA upgrade directly */ 236 /* */ 237 #define VERSION_NUMBER 0x01050025 /* Jason's first hacked version. */ 238 /* Change in download algorithm */ 239 240 #define DMA_VALID 0xb728e149 /* completely random */ 241 242 #define FLASH_BASE 0xa0c00000 243 #define FLASH_SIZE 0x00020000 /* 128K */ 244 #define BIA_BASE (FLASH_BASE+0x0001c000) /* Flash Sector 7 */ 245 #define BIA_ADDRESS ((void *)0xa0c1c000) 246 #define PLX_BASE 0xe0000000 247 248 typedef enum { 249 host_memory_test = 1, 250 read_adapter_memory, 251 write_adapter_memory, 252 adapter_start, 253 get_version_number, 254 interrupt_host, 255 flash_erase_sector, 256 adap_download_block = 0x20, 257 adap_erase_flash, 258 adap_run_in_iram, 259 adap_end_download 260 } loader_command; 261 262 #define BAD_COMMAND (-1) 263 #define COMMAND_IN_PROGRESS 1 264 #define COMMAND_PASSED_TEST 2 265 #define COMMAND_FAILED_TEST 3 266 #define COMMAND_READ_DATA_OK 4 267 #define COMMAND_READ_BAD_ADDRESS 5 268 #define COMMAND_WRITE_DATA_OK 6 269 #define COMMAND_WRITE_BAD_ADDRESS 7 270 #define COMMAND_WRITE_FLASH_FAILURE 8 271 #define COMMAND_COMPLETE 9 272 #define COMMAND_FLASH_ERASE_FAILURE 10 273 #define COMMAND_WRITE_BAD_DATA 11 274 275 /* bit fields for mailbox[0] return values */ 276 277 #define GPINT_TST_FAILURE 0x00000001 278 #define SUNI_DATA_PATTERN_FAILURE 0x00000002 279 #define SUNI_DATA_BITS_FAILURE 0x00000004 280 #define SUNI_UTOPIA_FAILURE 0x00000008 281 #define SUNI_FIFO_FAILURE 0x00000010 282 #define SRAM_FAILURE 0x00000020 283 #define SELF_TEST_FAILURE 0x0000003f 284 285 /* mailbox[1] = 0 in progress, -1 on completion */ 286 /* mailbox[2] = current test 00 00 test(8 bit) phase(8 bit) */ 287 /* mailbox[3] = last failure, 00 00 test(8 bit) phase(8 bit) */ 288 /* mailbox[4],mailbox[5],mailbox[6] random failure values */ 289 290 /* PLX/etc. memory map including command structure */ 291 292 /* These registers may also be memory mapped in PCI memory */ 293 294 #define UNUSED_LOADER_MAILBOXES 6 295 296 typedef struct { 297 u32 stuff[16]; 298 union { 299 struct { 300 u32 result; 301 u32 ready; 302 u32 stuff[UNUSED_LOADER_MAILBOXES]; 303 } loader; 304 struct { 305 u32 cmd_address; 306 u32 tx_address; 307 u32 rx_address[NUM_RX_POOLS]; 308 u32 gen_counter; 309 u32 spare; 310 } adapter; 311 } mb; 312 u32 doorbell; 313 u32 interrupt; 314 u32 interrupt_control; 315 u32 reset_control; 316 } amb_mem; 317 318 /* RESET bit, IRQ (card to host) and doorbell (host to card) enable bits */ 319 #define AMB_RESET_BITS 0x40000000 320 #define AMB_INTERRUPT_BITS 0x00000300 321 #define AMB_DOORBELL_BITS 0x00030000 322 323 /* loader commands */ 324 325 #define MAX_COMMAND_DATA 13 326 #define MAX_TRANSFER_DATA 11 327 328 typedef struct { 329 __be32 address; 330 __be32 count; 331 __be32 data[MAX_TRANSFER_DATA]; 332 } transfer_block; 333 334 typedef struct { 335 __be32 result; 336 __be32 command; 337 union { 338 transfer_block transfer; 339 __be32 version; 340 __be32 start; 341 __be32 data[MAX_COMMAND_DATA]; 342 } payload; 343 __be32 valid; 344 } loader_block; 345 346 /* command queue */ 347 348 /* Again all data are BIG ENDIAN */ 349 350 typedef struct { 351 union { 352 struct { 353 __be32 vc; 354 __be32 flags; 355 __be32 rate; 356 } open; 357 struct { 358 __be32 vc; 359 __be32 rate; 360 } modify_rate; 361 struct { 362 __be32 vc; 363 __be32 flags; 364 } modify_flags; 365 struct { 366 __be32 vc; 367 } close; 368 struct { 369 __be32 lower4; 370 __be32 upper2; 371 } bia; 372 struct { 373 __be32 address; 374 } suni; 375 struct { 376 __be32 major; 377 __be32 minor; 378 } version; 379 struct { 380 __be32 read; 381 __be32 write; 382 } speed; 383 struct { 384 __be32 flags; 385 } flush; 386 struct { 387 __be32 address; 388 __be32 data; 389 } memory; 390 __be32 par[3]; 391 } args; 392 __be32 request; 393 } command; 394 395 /* transmit queues and associated structures */ 396 397 /* The hosts transmit structure. All BIG ENDIAN; host address 398 restricted to first 1GByte, but address passed to the card must 399 have the top MS bit or'ed in. -- check this */ 400 401 /* TX is described by 1+ tx_frags followed by a tx_frag_end */ 402 403 typedef struct { 404 __be32 bytes; 405 __be32 address; 406 } tx_frag; 407 408 /* apart from handle the fields here are for the adapter to play with 409 and should be set to zero */ 410 411 typedef struct { 412 u32 handle; 413 u16 vc; 414 u16 next_descriptor_length; 415 u32 next_descriptor; 416 #ifdef AMB_NEW_MICROCODE 417 u8 cpcs_uu; 418 u8 cpi; 419 u16 pad; 420 #endif 421 } tx_frag_end; 422 423 typedef struct { 424 tx_frag tx_frag; 425 tx_frag_end tx_frag_end; 426 struct sk_buff * skb; 427 } tx_simple; 428 429 #if 0 430 typedef union { 431 tx_frag fragment; 432 tx_frag_end end_of_list; 433 } tx_descr; 434 #endif 435 436 /* this "points" to the sequence of fragments and trailer */ 437 438 typedef struct { 439 __be16 vc; 440 __be16 tx_descr_length; 441 __be32 tx_descr_addr; 442 } tx_in; 443 444 /* handle is the handle from tx_in */ 445 446 typedef struct { 447 u32 handle; 448 } tx_out; 449 450 /* receive frame structure */ 451 452 /* All BIG ENDIAN; handle is as passed from host; length is zero for 453 aborted frames, and frames with errors. Header is actually VC 454 number, lec-id is NOT yet supported. */ 455 456 typedef struct { 457 u32 handle; 458 __be16 vc; 459 __be16 lec_id; // unused 460 __be16 status; 461 __be16 length; 462 } rx_out; 463 464 /* buffer supply structure */ 465 466 typedef struct { 467 u32 handle; 468 __be32 host_address; 469 } rx_in; 470 471 /* This first structure is the area in host memory where the adapter 472 writes its pointer values. These pointer values are BIG ENDIAN and 473 reside in the same 4MB 'page' as this structure. The host gives the 474 adapter the address of this block by sending a doorbell interrupt 475 to the adapter after downloading the code and setting it going. The 476 addresses have the top 10 bits set to 1010000010b -- really? 477 478 The host must initialise these before handing the block to the 479 adapter. */ 480 481 typedef struct { 482 __be32 command_start; /* SRB commands completions */ 483 __be32 command_end; /* SRB commands completions */ 484 __be32 tx_start; 485 __be32 tx_end; 486 __be32 txcom_start; /* tx completions */ 487 __be32 txcom_end; /* tx completions */ 488 struct { 489 __be32 buffer_start; 490 __be32 buffer_end; 491 u32 buffer_q_get; 492 u32 buffer_q_end; 493 u32 buffer_aptr; 494 __be32 rx_start; /* rx completions */ 495 __be32 rx_end; 496 u32 rx_ptr; 497 __be32 buffer_size; /* size of host buffer */ 498 } rec_struct[NUM_RX_POOLS]; 499 #ifdef AMB_NEW_MICROCODE 500 u16 init_flags; 501 u16 talk_block_spare; 502 #endif 503 } adap_talk_block; 504 505 /* This structure must be kept in line with the vcr image in sarmain.h 506 507 This is the structure in the host filled in by the adapter by 508 GET_SUNI_STATS */ 509 510 typedef struct { 511 u8 racp_chcs; 512 u8 racp_uhcs; 513 u16 spare; 514 u32 racp_rcell; 515 u32 tacp_tcell; 516 u32 flags; 517 u32 dropped_cells; 518 u32 dropped_frames; 519 } suni_stats; 520 521 typedef enum { 522 dead 523 } amb_flags; 524 525 #define NEXTQ(current,start,limit) \ 526 ( (current)+1 < (limit) ? (current)+1 : (start) ) 527 528 typedef struct { 529 command * start; 530 command * in; 531 command * out; 532 command * limit; 533 } amb_cq_ptrs; 534 535 typedef struct { 536 spinlock_t lock; 537 unsigned int pending; 538 unsigned int high; 539 unsigned int filled; 540 unsigned int maximum; // size - 1 (q implementation) 541 amb_cq_ptrs ptrs; 542 } amb_cq; 543 544 typedef struct { 545 spinlock_t lock; 546 unsigned int pending; 547 unsigned int high; 548 unsigned int filled; 549 unsigned int maximum; // size - 1 (q implementation) 550 struct { 551 tx_in * start; 552 tx_in * ptr; 553 tx_in * limit; 554 } in; 555 struct { 556 tx_out * start; 557 tx_out * ptr; 558 tx_out * limit; 559 } out; 560 } amb_txq; 561 562 typedef struct { 563 spinlock_t lock; 564 unsigned int pending; 565 unsigned int low; 566 unsigned int emptied; 567 unsigned int maximum; // size - 1 (q implementation) 568 struct { 569 rx_in * start; 570 rx_in * ptr; 571 rx_in * limit; 572 } in; 573 struct { 574 rx_out * start; 575 rx_out * ptr; 576 rx_out * limit; 577 } out; 578 unsigned int buffers_wanted; 579 unsigned int buffer_size; 580 } amb_rxq; 581 582 typedef struct { 583 unsigned long tx_ok; 584 struct { 585 unsigned long ok; 586 unsigned long error; 587 unsigned long badcrc; 588 unsigned long toolong; 589 unsigned long aborted; 590 unsigned long unused; 591 } rx; 592 } amb_stats; 593 594 // a single struct pointed to by atm_vcc->dev_data 595 596 typedef struct { 597 u8 tx_vc_bits:7; 598 u8 tx_present:1; 599 } amb_tx_info; 600 601 typedef struct { 602 unsigned char pool; 603 } amb_rx_info; 604 605 typedef struct { 606 amb_rx_info rx_info; 607 u16 tx_frame_bits; 608 unsigned int tx_rate; 609 unsigned int rx_rate; 610 } amb_vcc; 611 612 struct amb_dev { 613 u8 irq; 614 unsigned long flags; 615 u32 iobase; 616 u32 * membase; 617 618 amb_cq cq; 619 amb_txq txq; 620 amb_rxq rxq[NUM_RX_POOLS]; 621 622 struct mutex vcc_sf; 623 amb_tx_info txer[NUM_VCS]; 624 struct atm_vcc * rxer[NUM_VCS]; 625 unsigned int tx_avail; 626 unsigned int rx_avail; 627 628 amb_stats stats; 629 630 struct atm_dev * atm_dev; 631 struct pci_dev * pci_dev; 632 struct timer_list housekeeping; 633 }; 634 635 typedef struct amb_dev amb_dev; 636 637 #define AMB_DEV(atm_dev) ((amb_dev *) (atm_dev)->dev_data) 638 #define AMB_VCC(atm_vcc) ((amb_vcc *) (atm_vcc)->dev_data) 639 640 /* rate rounding */ 641 642 typedef enum { 643 round_up, 644 round_down, 645 round_nearest 646 } rounding; 647 648 #endif 649