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Searched refs:reg32 (Results 1 – 18 of 18) sorted by relevance

/drivers/pci/pcie/
Daer.c138 u32 reg32; in enable_ecrc_checking() local
147 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32); in enable_ecrc_checking()
148 if (reg32 & PCI_ERR_CAP_ECRC_GENC) in enable_ecrc_checking()
149 reg32 |= PCI_ERR_CAP_ECRC_GENE; in enable_ecrc_checking()
150 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) in enable_ecrc_checking()
151 reg32 |= PCI_ERR_CAP_ECRC_CHKE; in enable_ecrc_checking()
152 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); in enable_ecrc_checking()
166 u32 reg32; in disable_ecrc_checking() local
175 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32); in disable_ecrc_checking()
176 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); in disable_ecrc_checking()
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Daspm.c176 u32 reg32; in pcie_clkpm_cap_init() local
183 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32); in pcie_clkpm_cap_init()
184 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { in pcie_clkpm_cap_init()
395 u32 reg32; in pcie_get_aspm_reg() local
397 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32); in pcie_get_aspm_reg()
398 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; in pcie_get_aspm_reg()
399 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; in pcie_get_aspm_reg()
400 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; in pcie_get_aspm_reg()
639 u32 reg32, encoding; in pcie_aspm_cap_init() local
647 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32); in pcie_aspm_cap_init()
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Dportdrv_core.c67 u32 reg32; in pcie_message_numbers() local
72 &reg32); in pcie_message_numbers()
73 *aer = (reg32 & PCI_ERR_ROOT_AER_IRQ) >> 27; in pcie_message_numbers()
/drivers/pci/
Dpci-acpi.c286 u32 reg32; in program_hpx_type2() local
336 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32); in program_hpx_type2()
337 reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or; in program_hpx_type2()
338 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); in program_hpx_type2()
341 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32); in program_hpx_type2()
342 reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or; in program_hpx_type2()
343 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); in program_hpx_type2()
346 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32); in program_hpx_type2()
347 reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or; in program_hpx_type2()
348 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); in program_hpx_type2()
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Dprobe.c1473 u32 reg32; in set_pcie_hotplug_bridge() local
1475 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32); in set_pcie_hotplug_bridge()
1476 if (reg32 & PCI_EXP_SLTCAP_HPC) in set_pcie_hotplug_bridge()
/drivers/infiniband/hw/hfi1/
Daspm.c49 u32 reg32; in aspm_hw_set_l1_ent_latency() local
51 pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, &reg32); in aspm_hw_set_l1_ent_latency()
52 reg32 &= ~PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK; in aspm_hw_set_l1_ent_latency()
53 reg32 |= l1_ent_lat << PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT; in aspm_hw_set_l1_ent_latency()
54 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, reg32); in aspm_hw_set_l1_ent_latency()
Dpcie.c988 u32 reg32, fs, lf; in do_pcie_gen3_transition() local
1110 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; in do_pcie_gen3_transition()
1111 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1120 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; in do_pcie_gen3_transition()
1121 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1379 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, &reg32); in do_pcie_gen3_transition()
1386 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
/drivers/net/wireless/ath/ath9k/
Dar9002_phy.c69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9002_hw_set_channel() local
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
77 reg32 &= 0xc0000000; in ar9002_hw_set_channel()
149 reg32 = reg32 | in ar9002_hw_set_channel()
153 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
Dar5008_phy.c87 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, in ar5008_hw_phy_modify_rx_buffer() argument
94 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); in ar5008_hw_phy_modify_rx_buffer()
187 u32 reg32 = 0; in ar5008_hw_set_channel() local
242 reg32 = in ar5008_hw_set_channel()
246 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
Dar9003_phy.c152 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; in ar9003_hw_set_channel() local
205 reg32 = (bMode << 29); in ar9003_hw_set_channel()
206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
213 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel()
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
219 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
Deeprom_4k.c296 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_4k_power_cal_table() local
360 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_4k_power_cal_table()
361 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table()
366 reg32); in ath9k_hw_set_4k_power_cal_table()
Deeprom_def.c778 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_def_power_cal_table() local
895 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_def_power_cal_table()
896 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table()
901 reg32); in ath9k_hw_set_def_power_cal_table()
Deeprom_9287.c365 u32 reg32, regOffset, regChainOffset, regval; in ath9k_hw_set_ar9287_power_cal_table() local
480 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_ar9287_power_cal_table()
482 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_ar9287_power_cal_table()
/drivers/ipack/carriers/
Dtpci200.c522 u32 reg32; in tpci200_pci_probe() local
556 reg32 = ioread32(tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe()
557 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe()
558 iowrite32(reg32, tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe()
560 reg32 = ioread32(tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
561 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe()
562 iowrite32(reg32, tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
/drivers/net/ethernet/freescale/fman/
Dfman_memac.c1036 u32 reg32 = 0; in memac_init() local
1077 reg32 = ioread32be(&memac->regs->command_config); in memac_init()
1078 reg32 &= ~CMD_CFG_CRC_FWD; in memac_init()
1079 iowrite32be(reg32, &memac->regs->command_config); in memac_init()
/drivers/net/wireless/realtek/rtl818x/rtl8180/
Ddev.c816 u32 reg32; in rtl8180_init_hw() local
967 reg32 = rtl818x_ioread32(priv, &priv->map->RF_PARA); in rtl8180_init_hw()
968 reg32 &= 0x00ffff00; in rtl8180_init_hw()
969 reg32 |= 0xb8000054; in rtl8180_init_hw()
970 rtl818x_iowrite32(priv, &priv->map->RF_PARA, reg32); in rtl8180_init_hw()
/drivers/net/wireless/realtek/rtl818x/rtl8187/
Ddev.c1533 u32 reg32; in rtl8187_probe() local
1534 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF); in rtl8187_probe()
1535 reg32 &= RTL818X_TX_CONF_HWVER_MASK; in rtl8187_probe()
1536 switch (reg32) { in rtl8187_probe()
/drivers/net/ethernet/broadcom/
Dtg3.c2557 u32 reg32, phy9_orig; in tg3_phy_reset_5703_4_5() local
2571 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) in tg3_phy_reset_5703_4_5()
2574 reg32 |= 0x3000; in tg3_phy_reset_5703_4_5()
2575 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2613 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32); in tg3_phy_reset_5703_4_5()
2617 reg32 &= ~0x3000; in tg3_phy_reset_5703_4_5()
2618 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()