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Searched refs:reg_shift (Results 1 – 25 of 30) sorted by relevance

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/drivers/gpio/
Dgpio-adnp.c14 #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
15 #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
16 #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
17 #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
18 #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
23 unsigned int reg_shift; member
68 unsigned int reg = offset >> adnp->reg_shift; in adnp_gpio_get()
82 unsigned int reg = offset >> adnp->reg_shift; in __adnp_gpio_set()
111 unsigned int reg = offset >> adnp->reg_shift; in adnp_gpio_direction_input()
148 unsigned int reg = offset >> adnp->reg_shift; in adnp_gpio_direction_output()
[all …]
Dgpio-creg-snps.c34 u32 reg, reg_shift, value; in creg_gpio_set() local
40 reg_shift = layout->shift[offset]; in creg_gpio_set()
42 reg_shift += layout->bit_per_gpio[i] + layout->shift[i]; in creg_gpio_set()
46 reg &= ~(GENMASK(layout->bit_per_gpio[i] - 1, 0) << reg_shift); in creg_gpio_set()
47 reg |= (value << reg_shift); in creg_gpio_set()
Dgpio-htc-egpio.c37 int reg_shift; /* bit shift */ member
123 return bit >> ei->reg_shift; in egpio_pos()
128 return 1 << (bit & ((1 << ei->reg_shift)-1)); in egpio_bit()
189 shift = pos << ei->reg_shift; in egpio_set()
238 shift += (1<<ei->reg_shift)) { in egpio_write_cache()
300 ei->reg_shift = fls(pdata->reg_width - 1); in egpio_probe()
301 pr_debug("reg_shift = %d\n", ei->reg_shift); in egpio_probe()
/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-socfpga.c50 u32 reg_shift; member
104 u32 reg_offset, reg_shift; in socfpga_dwmac_parse_data() local
125 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, &reg_shift); in socfpga_dwmac_parse_data()
219 dwmac->reg_shift = reg_shift; in socfpga_dwmac_parse_data()
265 u32 reg_shift = dwmac->reg_shift; in socfpga_gen5_set_phy_mode() local
285 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); in socfpga_gen5_set_phy_mode()
286 ctrl |= val << reg_shift; in socfpga_gen5_set_phy_mode()
292 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); in socfpga_gen5_set_phy_mode()
295 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); in socfpga_gen5_set_phy_mode()
299 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2)); in socfpga_gen5_set_phy_mode()
[all …]
Dstmmac_mdio.c167 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_read()
176 priv->hw->mii.reg_shift) & in stmmac_mdio_read()
222 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; in stmmac_mdio_write()
232 priv->hw->mii.reg_shift) & in stmmac_mdio_write()
Dcommon.h427 unsigned int reg_shift; /* MII reg shift */ member
456 u32 reg_shift; member
Ddwmac100_core.c195 mac->mii.reg_shift = 6; in dwmac100_setup()
Ddwmac4_core.c131 value |= (queue << route_possibilities[packet-1].reg_shift) & in dwmac4_rx_queue_routing()
939 mac->mii.reg_shift = 16; in dwmac4_setup()
Ddwmac1000_core.c557 mac->mii.reg_shift = 6; in dwmac1000_setup()
/drivers/ata/
Dpata_pxa.c234 (ATA_REG_DATA << pdata->reg_shift); in pxa_ata_probe()
236 (ATA_REG_ERR << pdata->reg_shift); in pxa_ata_probe()
238 (ATA_REG_FEATURE << pdata->reg_shift); in pxa_ata_probe()
240 (ATA_REG_NSECT << pdata->reg_shift); in pxa_ata_probe()
242 (ATA_REG_LBAL << pdata->reg_shift); in pxa_ata_probe()
244 (ATA_REG_LBAM << pdata->reg_shift); in pxa_ata_probe()
246 (ATA_REG_LBAH << pdata->reg_shift); in pxa_ata_probe()
248 (ATA_REG_DEVICE << pdata->reg_shift); in pxa_ata_probe()
250 (ATA_REG_STATUS << pdata->reg_shift); in pxa_ata_probe()
252 (ATA_REG_CMD << pdata->reg_shift); in pxa_ata_probe()
Dpata_of_platform.c29 unsigned int reg_shift = 0; in pata_of_platform_probe() local
50 of_property_read_u32(dn, "reg-shift", &reg_shift); in pata_of_platform_probe()
67 reg_shift, pio_mask, &pata_platform_sht, in pata_of_platform_probe()
/drivers/i2c/busses/
Di2c-ocores.c36 u32 reg_shift; member
92 iowrite8(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_8()
97 iowrite16(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16()
102 iowrite32(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32()
107 iowrite16be(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_16be()
112 iowrite32be(value, i2c->base + (reg << i2c->reg_shift)); in oc_setreg_32be()
117 return ioread8(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_8()
122 return ioread16(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_16()
127 return ioread32(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_32()
132 return ioread16be(i2c->base + (reg << i2c->reg_shift)); in oc_getreg_16be()
[all …]
Di2c-omap.c182 int reg_shift; /* bit shift for I2C register addresses */ member
269 (omap->regs[reg] << omap->reg_shift)); in omap_i2c_write_reg()
275 (omap->regs[reg] << omap->reg_shift)); in omap_i2c_read_reg()
1405 omap->reg_shift = (omap->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; in omap_i2c_probe()
/drivers/thermal/broadcom/
Dbrcmstb_thermal.c75 int reg_shift; member
85 .reg_shift = AVS_TMON_INT_THRESH_low_shift,
93 .reg_shift = AVS_TMON_INT_THRESH_high_shift,
101 .reg_shift = AVS_TMON_RESET_THRESH_shift,
202 val >>= trip->reg_shift; in avs_tmon_get_trip_temp()
220 val <<= trip->reg_shift; in avs_tmon_set_trip_temp()
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_vbif.c159 u32 reg_val, reg_val_lvl, mask, reg_high, reg_shift; in dpu_hw_set_qos_remap() local
167 reg_shift = (xin_id & 0x7) * 4; in dpu_hw_set_qos_remap()
172 mask = 0x7 << reg_shift; in dpu_hw_set_qos_remap()
175 reg_val |= (remap_level << reg_shift) & mask; in dpu_hw_set_qos_remap()
178 reg_val_lvl |= (remap_level << reg_shift) & mask; in dpu_hw_set_qos_remap()
/drivers/pinctrl/
Dpinctrl-mcp23s08.c61 bool reg_shift; member
172 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); in mcp_read()
177 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); in mcp_write()
184 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, in mcp_set_mask()
693 mcp->reg_shift = 0; in mcp23s08_probe_one()
702 mcp->reg_shift = 1; in mcp23s08_probe_one()
724 mcp->reg_shift = 1; in mcp23s08_probe_one()
733 mcp->reg_shift = 0; in mcp23s08_probe_one()
740 mcp->reg_shift = 1; in mcp23s08_probe_one()
747 mcp->reg_shift = 1; in mcp23s08_probe_one()
/drivers/tty/serial/8250/
D8250_pci.c137 return setup_port(priv, port, bar, offset, board->reg_shift); in addidata_apci7800_setup()
158 return setup_port(priv, port, bar, offset, board->reg_shift); in afavlab_setup()
223 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_hp_diva_setup()
385 return setup_port(priv, port, bar, offset, board->reg_shift); in sbs_setup()
644 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_timedia_setup()
669 return setup_port(priv, port, bar, offset, board->reg_shift); in titan_400l_800l_setup()
776 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_ni8430_setup()
792 return setup_port(priv, port, bar, 0, board->reg_shift); in pci_netmos_9900_setup()
1337 (board->reg_shift + 3); in pci_default_setup()
1342 return setup_port(priv, port, bar, offset, board->reg_shift); in pci_default_setup()
[all …]
D8250_exar.c120 unsigned int reg_shift; member
200 port->port.regshift = board->reg_shift; in default_setup()
560 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); in exar_pci_probe()
/drivers/ssb/
Ddriver_extif.c77 ports[i].reg_shift = 0; in ssb_extif_serial_init()
/drivers/base/regmap/
Dinternal.h114 int reg_shift; member
Dregmap.c773 map->reg_shift = config->pad_bits % 8; in __regmap_init()
841 switch (config->reg_bits + map->reg_shift) { in __regmap_init()
1549 map->format.format_reg(map->work_buf, reg, map->reg_shift); in _regmap_raw_write_impl()
2156 map->format.format_reg(u8, reg, map->reg_shift); in _regmap_raw_multi_reg_write()
2475 map->format.format_reg(map->work_buf, reg, map->reg_shift); in _regmap_raw_read()
/drivers/gpu/drm/bridge/synopsys/
Ddw-hdmi.c188 unsigned int reg_shift; member
207 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); in hdmi_writeb()
214 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); in hdmi_readb()
221 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); in hdmi_modb()
2658 hdmi->reg_shift = 2; in __dw_hdmi_probe()
/drivers/bcma/
Ddriver_chipcommon.c418 ports[i].reg_shift = 0; in bcma_chipco_serial_init()
/drivers/mmc/host/
Domap.c79 #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
135 unsigned int reg_shift; member
1426 host->reg_shift = (mmc_omap7xx() ? 1 : 2); in mmc_omap_probe()
/drivers/hwmon/
Dw83795.c1442 int reg_shift; in store_temp_mode() local
1462 reg_shift = 2 * index; in store_temp_mode()
1464 tmp &= ~(0x03 << reg_shift); in store_temp_mode()
1465 tmp |= val << reg_shift; in store_temp_mode()

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