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Searched refs:rptr (Results 1 – 25 of 67) sorted by relevance

123

/drivers/gpu/drm/radeon/
Dradeon_ring.c84 uint32_t rptr = radeon_ring_get_rptr(rdev, ring); in radeon_ring_free_size() local
87 ring->ring_free_dw = rptr + (ring->ring_size / 4); in radeon_ring_free_size()
253 uint32_t rptr = radeon_ring_get_rptr(rdev, ring); in radeon_ring_test_lockup() local
257 if (rptr != atomic_read(&ring->last_rptr)) { in radeon_ring_test_lockup()
472 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info() local
482 rptr = radeon_ring_get_rptr(rdev, ring); in radeon_debugfs_ring_info()
484 rptr, rptr); in radeon_debugfs_ring_info()
508 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask; in radeon_debugfs_ring_info()
511 if (rptr == i) in radeon_debugfs_ring_info()
Dni_dma.c56 u32 rptr, reg; in cayman_dma_get_rptr() local
59 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_dma_get_rptr()
66 rptr = RREG32(reg); in cayman_dma_get_rptr()
69 return (rptr & 0x3fffc) >> 2; in cayman_dma_get_rptr()
Dr600_dma.c54 u32 rptr; in r600_dma_get_rptr() local
57 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
59 rptr = RREG32(DMA_RB_RPTR); in r600_dma_get_rptr()
61 return (rptr & 0x3fffc) >> 2; in r600_dma_get_rptr()
/drivers/gpu/drm/amd/amdgpu/
Dvega10_ih.c122 adev->irq.ih.rptr = 0; in vega10_ih_disable_interrupts()
141 adev->irq.ih1.rptr = 0; in vega10_ih_disable_interrupts()
162 adev->irq.ih2.rptr = 0; in vega10_ih_disable_interrupts()
407 wptr, ih->rptr, tmp); in vega10_ih_get_wptr()
408 ih->rptr = tmp; in vega10_ih_get_wptr()
440 u32 ring_index = ih->rptr >> 2; in vega10_ih_decode_iv()
467 ih->rptr += 32; in vega10_ih_decode_iv()
495 if ((v < ih->ring_size) && (v != ih->rptr)) in vega10_ih_irq_rearm()
496 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega10_ih_irq_rearm()
514 *ih->rptr_cpu = ih->rptr; in vega10_ih_set_rptr()
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Damdgpu_ih.c52 ih->rptr = 0; in amdgpu_ih_ring_init()
159 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); in amdgpu_ih_process()
164 while (ih->rptr != wptr && --count) { in amdgpu_ih_process()
166 ih->rptr &= ih->ptr_mask; in amdgpu_ih_process()
174 if (wptr != ih->rptr) in amdgpu_ih_process()
Dtonga_ih.c88 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
205 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in tonga_ih_get_wptr()
206 ih->rptr = (wptr + 16) & ih->ptr_mask; in tonga_ih_get_wptr()
227 u32 ring_index = ih->rptr >> 2; in tonga_ih_decode_iv()
243 ih->rptr += 16; in tonga_ih_decode_iv()
258 *ih->rptr_cpu = ih->rptr; in tonga_ih_set_rptr()
259 WDOORBELL32(ih->doorbell_index, ih->rptr); in tonga_ih_set_rptr()
261 WREG32(mmIH_RB_RPTR, ih->rptr); in tonga_ih_set_rptr()
Dnavi10_ih.c73 adev->irq.ih.rptr = 0; in navi10_ih_disable_interrupts()
233 wptr, ih->rptr, tmp); in navi10_ih_get_wptr()
234 ih->rptr = tmp; in navi10_ih_get_wptr()
257 u32 ring_index = ih->rptr >> 2; in navi10_ih_decode_iv()
284 ih->rptr += 32; in navi10_ih_decode_iv()
299 *ih->rptr_cpu = ih->rptr; in navi10_ih_set_rptr()
300 WDOORBELL32(ih->doorbell_index, ih->rptr); in navi10_ih_set_rptr()
302 WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, ih->rptr); in navi10_ih_set_rptr()
Dsi_ih.c57 adev->irq.ih.rptr = 0; in si_ih_disable_interrupts()
115 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
116 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
128 u32 ring_index = ih->rptr >> 2; in si_ih_decode_iv()
142 ih->rptr += 16; in si_ih_decode_iv()
148 WREG32(IH_RB_RPTR, ih->rptr); in si_ih_set_rptr()
Dcik_ih.c92 adev->irq.ih.rptr = 0; in cik_ih_disable_interrupts()
201 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
202 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
246 u32 ring_index = ih->rptr >> 2; in cik_ih_decode_iv()
262 ih->rptr += 16; in cik_ih_decode_iv()
275 WREG32(mmIH_RB_RPTR, ih->rptr); in cik_ih_set_rptr()
Diceland_ih.c92 adev->irq.ih.rptr = 0; in iceland_ih_disable_interrupts()
203 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in iceland_ih_get_wptr()
204 ih->rptr = (wptr + 16) & ih->ptr_mask; in iceland_ih_get_wptr()
225 u32 ring_index = ih->rptr >> 2; in iceland_ih_decode_iv()
241 ih->rptr += 16; in iceland_ih_decode_iv()
254 WREG32(mmIH_RB_RPTR, ih->rptr); in iceland_ih_set_rptr()
Dcz_ih.c92 adev->irq.ih.rptr = 0; in cz_ih_disable_interrupts()
203 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cz_ih_get_wptr()
204 ih->rptr = (wptr + 16) & ih->ptr_mask; in cz_ih_get_wptr()
225 u32 ring_index = ih->rptr >> 2; in cz_ih_decode_iv()
241 ih->rptr += 16; in cz_ih_decode_iv()
254 WREG32(mmIH_RB_RPTR, ih->rptr); in cz_ih_set_rptr()
/drivers/infiniband/hw/cxgb3/
Dcxio_wr.h46 #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr)) argument
47 #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \ argument
48 ((rptr)!=(wptr)) )
50 #define Q_FREECNT(rptr,wptr,size_log2) ((1UL<<size_log2)-((wptr)-(rptr))) argument
51 #define Q_COUNT(rptr,wptr) ((wptr)-(rptr)) argument
717 u32 rptr; member
771 cqe = cq->queue + (Q_PTR2IDX(cq->rptr, cq->size_log2)); in cxio_next_hw_cqe()
772 if (CQ_VLD_ENTRY(cq->rptr, cq->size_log2, cqe)) in cxio_next_hw_cqe()
796 cqe = cq->queue + (Q_PTR2IDX(cq->rptr, cq->size_log2)); in cxio_next_cqe()
797 if (CQ_VLD_ENTRY(cq->rptr, cq->size_log2, cqe)) in cxio_next_cqe()
Dcxio_hal.c76 u32 rptr; in cxio_hal_cq_op() local
92 if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) { in cxio_hal_cq_op()
95 rptr = cq->rptr; in cxio_hal_cq_op()
101 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret) in cxio_hal_cq_op()
102 rptr++; in cxio_hal_cq_op()
109 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2); in cxio_hal_cq_op()
110 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) { in cxio_hal_cq_op()
414 __func__, cq->rptr, cq->sw_wptr); in cxio_flush_hw_cq()
419 cq->rptr++; in cxio_flush_hw_cq()
584 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len, in cxio_hal_ctrl_qp_write_mem()
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/drivers/net/ethernet/tehuti/
Dtehuti.c167 f->rptr = 0; in bdx_fifo_init()
1213 size = f->m.wptr - f->m.rptr; in bdx_rx_receive()
1219 rxdd = (struct rxd_desc *)(f->m.va + f->m.rptr); in bdx_rx_receive()
1234 f->m.rptr += tmp_len; in bdx_rx_receive()
1236 tmp_len = f->m.rptr - f->m.memsz; in bdx_rx_receive()
1238 f->m.rptr = tmp_len; in bdx_rx_receive()
1241 f->m.rptr, tmp_len); in bdx_rx_receive()
1295 WRITE_REG(priv, f->m.reg_RPTR, f->m.rptr & TXF_WPTR_WR_PTR); in bdx_rx_receive()
1370 int taken = db->wptr - db->rptr; in bdx_tx_db_size()
1386 BDX_ASSERT(*pptr != db->rptr && /* expect either read */ in __bdx_tx_db_ptr_next()
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/drivers/video/fbdev/
Dmaxinefb.c77 unsigned char *rptr; in maxinefb_ims332_read_register() local
80 rptr = regs + 0x80000 + (regno << 4); in maxinefb_ims332_read_register()
81 j = *((volatile unsigned short *) rptr); in maxinefb_ims332_read_register()
/drivers/gpu/drm/qxl/
Dqxl_object.c152 void *rptr; in qxl_bo_kmap_atomic_page() local
170 rptr = bo->kptr + (page_offset * PAGE_SIZE); in qxl_bo_kmap_atomic_page()
171 return rptr; in qxl_bo_kmap_atomic_page()
174 ret = qxl_bo_kmap(bo, &rptr); in qxl_bo_kmap_atomic_page()
178 rptr += page_offset * PAGE_SIZE; in qxl_bo_kmap_atomic_page()
179 return rptr; in qxl_bo_kmap_atomic_page()
/drivers/net/ppp/
Dppp_deflate.c46 static int z_compress(void *state, unsigned char *rptr,
185 static int z_compress(void *arg, unsigned char *rptr, unsigned char *obuf, in z_compress() argument
195 proto = PPP_PROTOCOL(rptr); in z_compress()
209 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
210 wptr[1] = PPP_CONTROL(rptr); in z_compress()
221 rptr += off; in z_compress()
222 state->strm.next_in = rptr; in z_compress()
Dbsd_comp.c184 static int bsd_compress (void *state, unsigned char *rptr,
563 static int bsd_compress (void *state, unsigned char *rptr, unsigned char *obuf, in bsd_compress() argument
615 ent = PPP_PROTOCOL(rptr); in bsd_compress()
641 *wptr++ = PPP_ADDRESS(rptr); in bsd_compress()
642 *wptr++ = PPP_CONTROL(rptr); in bsd_compress()
650 rptr += PPP_HDRLEN; in bsd_compress()
656 c = *rptr++; in bsd_compress()
/drivers/i2c/busses/
Di2c-cpm.c302 int rptr; in cpm_i2c_xfer() local
314 rptr = 0; in cpm_i2c_xfer()
326 dev_dbg(&adap->dev, "R: %d T: %d\n", rptr, tptr); in cpm_i2c_xfer()
328 cpm_i2c_parse_message(adap, pmsg, num, tptr, rptr); in cpm_i2c_xfer()
330 rptr++; in cpm_i2c_xfer()
343 rptr = 0; in cpm_i2c_xfer()
352 !(in_be16(&rbdf[rptr].cbd_sc) & BD_SC_EMPTY), in cpm_i2c_xfer()
365 ret = cpm_i2c_check_message(adap, pmsg, tptr, rptr); in cpm_i2c_xfer()
368 rptr++; in cpm_i2c_xfer()
/drivers/gpu/drm/amd/amdkfd/
Dkfd_kernel_queue.c215 uint32_t wptr, rptr; in acquire_packet_buffer() local
224 rptr = *kq->rptr_kernel; in acquire_packet_buffer()
230 pr_debug("rptr: %d\n", rptr); in acquire_packet_buffer()
234 available_size = (rptr + queue_size_dwords - 1 - wptr) % in acquire_packet_buffer()
249 if (packet_size_in_dwords >= rptr) in acquire_packet_buffer()
/drivers/net/ethernet/cavium/liquidio/
Docteon_iq.h195 u64 rptr; member
226 u64 rptr; member
253 u64 rptr; member
Docteon_nic.c74 sc->cmd.cmd3.rptr = sc->dmarptr; in octeon_alloc_soft_command_resp()
76 sc->cmd.cmd2.rptr = sc->dmarptr; in octeon_alloc_soft_command_resp()
/drivers/gpu/drm/msm/adreno/
Dadreno_gpu.c354 ring->memptrs->rptr = 0; in adreno_hw_init()
374 rbmemptr(gpu->rb[0], rptr)); in adreno_hw_init()
385 return ring->memptrs->rptr = adreno_gpu_read( in get_rptr()
388 return ring->memptrs->rptr; in get_rptr()
538 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); in adreno_gpu_state_get()
718 drm_printf(p, " rptr: %d\n", state->ring[i].rptr); in adreno_show()
808 uint32_t rptr = get_rptr(adreno_gpu, ring); in ring_freewords() local
809 return (rptr + (size - 1) - wptr) % size; in ring_freewords()
Da5xx_preempt.c66 empty = (get_wptr(ring) == ring->memptrs->rptr); in get_next_ring()
211 a5xx_gpu->preempt[i]->rptr = 0; in a5xx_preempt_hw_init()
251 ptr->rptr_addr = rbmemptr(ring, rptr); in preempt_init_ring()
/drivers/tty/
Dmoxa.c270 u16 rptr, wptr, mask, len; in moxa_low_water_check() local
273 rptr = readw(ofsAddr + RXrptr); in moxa_low_water_check()
276 len = (wptr - rptr) & mask; in moxa_low_water_check()
1989 u16 rptr, wptr, mask; in MoxaPortTxQueue() local
1991 rptr = readw(ofsAddr + TXrptr); in MoxaPortTxQueue()
1994 return (wptr - rptr) & mask; in MoxaPortTxQueue()
2000 u16 rptr, wptr, mask; in MoxaPortTxFree() local
2002 rptr = readw(ofsAddr + TXrptr); in MoxaPortTxFree()
2005 return mask - ((wptr - rptr) & mask); in MoxaPortTxFree()
2011 u16 rptr, wptr, mask; in MoxaPortRxQueue() local
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