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Searched refs:rq_regs_l (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubp.c130 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp21_program_requestor()
131 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp21_program_requestor()
132 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp21_program_requestor()
133 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp21_program_requestor()
134 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, in hubp21_program_requestor()
135 VM_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, in hubp21_program_requestor()
136 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp21_program_requestor()
137 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); in hubp21_program_requestor()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hubp.c556 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp1_program_requestor()
557 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp1_program_requestor()
558 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp1_program_requestor()
559 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp1_program_requestor()
560 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, in hubp1_program_requestor()
561 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, in hubp1_program_requestor()
562 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp1_program_requestor()
563 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); in hubp1_program_requestor()
1027 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp1_read_state()
1028 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, in hubp1_read_state()
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Ddcn10_hw_sequencer_debug.c213 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size, in dcn10_get_rq_states()
214 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, in dcn10_get_rq_states()
215 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size, in dcn10_get_rq_states()
216 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, in dcn10_get_rq_states()
217 …rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_ch… in dcn10_get_rq_states()
Ddcn10_hw_sequencer.c174 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size, in dcn10_log_hubp_states()
175 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size, in dcn10_log_hubp_states()
176 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size, in dcn10_log_hubp_states()
177 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height, in dcn10_log_hubp_states()
178 …rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_ch… in dcn10_log_hubp_states()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubp.c204 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size, in hubp2_program_requestor()
205 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size, in hubp2_program_requestor()
206 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size, in hubp2_program_requestor()
207 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size, in hubp2_program_requestor()
208 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size, in hubp2_program_requestor()
209 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size, in hubp2_program_requestor()
210 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height, in hubp2_program_requestor()
211 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear); in hubp2_program_requestor()
1225 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size, in hubp2_read_state()
1226 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size, in hubp2_read_state()
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/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_rq_dlg_helpers.c183 print__data_rq_regs_st(mode_lib, rq_regs.rq_regs_l); in print__rq_regs_st()
Ddisplay_mode_structs.h495 display_data_rq_regs_st rq_regs_l; member
Ddml1_display_rq_dlg_calc.c239 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); in dml1_extract_rq_regs()
243 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); in dml1_extract_rq_regs()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20v2.c196 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); in extract_rq_regs()
198 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), in extract_rq_regs()
207 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); in extract_rq_regs()
Ddisplay_rq_dlg_calc_20.c196 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); in extract_rq_regs()
198 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), in extract_rq_regs()
207 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); in extract_rq_regs()
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c175 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); in extract_rq_regs()
177 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor( in extract_rq_regs()
188 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); in extract_rq_regs()