Searched refs:sandybridge_pcode_write (Results 1 – 6 of 6) sorted by relevance
| /drivers/gpu/drm/i915/ |
| D | intel_sideband.h | 135 #define sandybridge_pcode_write(i915, mbox, val) \ macro
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| D | intel_pm.c | 3692 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, in intel_enable_sagv()
7446 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); in gen6_enable_rc6()
7552 sandybridge_pcode_write(dev_priv, in gen6_update_ring_freq()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 729 ret = sandybridge_pcode_write(dev_priv, in bdw_set_cdclk()
779 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
1076 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1672 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in cnl_set_cdclk()
1849 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, in icl_set_cdclk()
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| D | intel_hdcp.c | 218 ret = sandybridge_pcode_write(dev_priv, in intel_hdcp_load_keys()
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| D | intel_display_power.c | 4289 if (sandybridge_pcode_write(dev_priv, in hsw_write_dcomp()
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| D | intel_display.c | 5686 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, in hsw_enable_ips()
5715 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); in hsw_disable_ips()
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