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Searched refs:sclk_dpm_enable_mask (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/powerplay/hwmgr/
Dsmu7_hwmgr.h167 uint32_t sclk_dpm_enable_mask; member
Dvega10_hwmgr.h177 uint32_t sclk_dpm_enable_mask; member
Dvega12_hwmgr.h155 uint32_t sclk_dpm_enable_mask; member
Dsmu7_hwmgr.c2618 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_force_dpm_highest()
2620 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; in smu7_force_dpm_highest()
2657 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) in smu7_upload_dpm_level_enable_mask()
2660 data->dpm_level_enable_mask.sclk_dpm_enable_mask); in smu7_upload_dpm_level_enable_mask()
2695 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_force_dpm_lowest()
2697 data->dpm_level_enable_mask.sclk_dpm_enable_mask); in smu7_force_dpm_lowest()
3860 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in smu7_generate_dpm_level_enable_mask()
4409 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); in smu7_force_clock_level()
4985 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { in smu7_patch_compute_profile_mode()
4987 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; in smu7_patch_compute_profile_mode()
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Dvega20_hwmgr.h208 uint32_t sclk_dpm_enable_mask; member
/drivers/gpu/drm/radeon/
Dci_dpm.h111 u32 sclk_dpm_enable_mask; member
Dci_dpm.c3305 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3823 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3826 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
4178 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4234 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4236 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4273 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4275 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
/drivers/gpu/drm/amd/powerplay/smumgr/
Dvegam_smumgr.c907 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in vegam_populate_all_graphic_levels()
912 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1; in vegam_populate_all_graphic_levels()
Diceland_smumgr.c1002 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in iceland_populate_all_graphic_levels()
Dfiji_smumgr.c1047 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in fiji_populate_all_graphic_levels()
Dpolaris10_smumgr.c1020 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask = in polaris10_populate_all_graphic_levels()
Dtonga_smumgr.c732 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in tonga_populate_all_graphic_levels()
Dci_smumgr.c500 data->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()