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Searched refs:skl (Results 1 – 7 of 7) sorted by relevance

/drivers/edac/
Die31200_edac.c169 #define IE31200_PAGES(n, skl) \ argument
170 (n << (28 + (2 * skl) - PAGE_SHIFT))
386 bool skl) in populate_dimm_info() argument
388 if (skl) in populate_dimm_info()
409 bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device); in ie31200_probe1() local
438 if (skl) in ie31200_probe1()
451 if (skl) { in ie31200_probe1()
468 skl); in ie31200_probe1()
487 nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl); in ie31200_probe1()
499 if (skl) in ie31200_probe1()
[all …]
/drivers/gpu/drm/i915/display/
Dintel_atomic_plane.c248 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_next_plane_to_commit()
251 skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id], in skl_next_plane_to_commit()
257 entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_next_plane_to_commit()
258 entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id]; in skl_next_plane_to_commit()
310 memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y, in skl_update_planes_on_crtc()
311 sizeof(old_crtc_state->wm.skl.plane_ddb_y)); in skl_update_planes_on_crtc()
312 memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv, in skl_update_planes_on_crtc()
313 sizeof(old_crtc_state->wm.skl.plane_ddb_uv)); in skl_update_planes_on_crtc()
Dintel_display_types.h705 } skl; member
Dintel_display.c12899 sw_wm = &new_crtc_state->wm.skl.optimal; in verify_wm_state()
12949 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane]; in verify_wm_state()
13001 sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; in verify_wm_state()
13803 entries[i] = old_crtc_state->wm.skl.ddb; in skl_update_crtcs()
13827 if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, in skl_update_crtcs()
13833 entries[i] = new_crtc_state->wm.skl.ddb; in skl_update_crtcs()
13841 if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, in skl_update_crtcs()
13842 &old_crtc_state->wm.skl.ddb) && in skl_update_crtcs()
/drivers/gpu/drm/i915/
Dintel_pm.c3792 &crtc_state->wm.skl.optimal.planes[plane->id]; in intel_can_enable_sagv()
3903 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; in skl_ddb_get_pipe_allocation_limits()
4341 struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb; in skl_allocate_pipe_ddb()
4354 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); in skl_allocate_pipe_ddb()
4355 memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv)); in skl_allocate_pipe_ddb()
4385 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start = in skl_allocate_pipe_ddb()
4387 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end; in skl_allocate_pipe_ddb()
4400 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_allocate_pipe_ddb()
4435 &crtc_state->wm.skl.optimal.planes[plane_id]; in skl_allocate_pipe_ddb()
4474 &crtc_state->wm.skl.plane_ddb_y[plane_id]; in skl_allocate_pipe_ddb()
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Di915_debugfs.c2976 entry = &crtc_state->wm.skl.plane_ddb_y[plane_id]; in i915_ddb_info()
2982 entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; in i915_ddb_info()
/drivers/gpu/drm/i915/gt/uc/
Dintel_uc_fw.c47 fw_def(SKYLAKE, 0, guc_def(skl, 33, 0, 0), huc_def(skl, 01, 07, 1398))