| /drivers/clk/ti/ |
| D | clkctrl.c | 453 u16 soc_mask = 0; in _ti_omap4_clkctrl_setup() local
479 soc_mask = CLKF_SOC_DRA72; in _ti_omap4_clkctrl_setup()
481 soc_mask = CLKF_SOC_DRA74; in _ti_omap4_clkctrl_setup()
483 soc_mask = CLKF_SOC_DRA76; in _ti_omap4_clkctrl_setup()
517 soc_mask |= CLKF_SOC_NONSEC; in _ti_omap4_clkctrl_setup()
581 (reg_data->flags & soc_mask) == 0) { in _ti_omap4_clkctrl_setup()
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| /drivers/pinctrl/ |
| D | pinctrl-single.c | 1375 unsigned soc_mask; in pcs_irq_set() local
1381 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1385 mask |= soc_mask; in pcs_irq_set()
1387 mask &= ~soc_mask; in pcs_irq_set()
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| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 1583 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1592 *soc_mask = 0; in vega12_get_profiling_clk_mask()
1599 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL; in vega12_get_profiling_clk_mask()
1609 *soc_mask = soc_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1639 uint32_t soc_mask = 0; in vega12_dpm_force_dpm_level() local
1655 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
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| D | vega20_hwmgr.c | 2474 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2483 *soc_mask = 0; in vega20_get_profiling_clk_mask()
2490 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL; in vega20_get_profiling_clk_mask()
2500 *soc_mask = soc_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2673 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2692 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2697 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask); in vega20_dpm_force_dpm_level()
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| D | vega10_hwmgr.c | 4032 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4041 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL; in vega10_get_profiling_clk_mask()
4053 *soc_mask = table_info->vdd_dep_on_socclk->count - 1; in vega10_get_profiling_clk_mask()
4143 uint32_t soc_mask = 0; in vega10_dpm_force_dpm_level() local
4146 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4162 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
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| /drivers/gpu/drm/amd/powerplay/ |
| D | amdgpu_smu.c | 1572 uint32_t sclk_mask, mclk_mask, soc_mask; in smu_default_set_performance_level() local
1591 &soc_mask); in smu_default_set_performance_level()
1596 smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); in smu_default_set_performance_level()
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| D | arcturus_ppt.c | 1293 uint32_t *soc_mask) in arcturus_get_profiling_clk_mask() argument
1310 *soc_mask = 0; in arcturus_get_profiling_clk_mask()
1317 *soc_mask = ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL; in arcturus_get_profiling_clk_mask()
1327 *soc_mask = soc_dpm_table->count - 1; in arcturus_get_profiling_clk_mask()
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| D | navi10_ppt.c | 1216 uint32_t *soc_mask) in navi10_get_profiling_clk_mask() argument
1242 if(soc_mask) { in navi10_get_profiling_clk_mask()
1246 *soc_mask = level_count - 1; in navi10_get_profiling_clk_mask()
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| D | vega20_ppt.c | 1990 uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2006 *soc_mask = 0; in vega20_get_profiling_clk_mask()
2013 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL; in vega20_get_profiling_clk_mask()
2023 *soc_mask = soc_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
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| /drivers/gpu/drm/amd/powerplay/inc/ |
| D | amdgpu_smu.h | 444 uint32_t *soc_mask);
674 #define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask) \ argument
675 …(smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask), (mclk_mask), (soc_mask)) : 0)
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