Home
last modified time | relevance | path

Searched refs:src_h (Results 1 – 25 of 76) sorted by relevance

1234

/drivers/media/platform/ti-vpe/
Dsc.c110 void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h, in sc_set_vs_coeffs() argument
119 if (dst_h > src_h) { in sc_set_vs_coeffs()
121 } else if (dst_h == src_h) { in sc_set_vs_coeffs()
124 sixteenths = (dst_h << 4) / src_h; in sc_set_vs_coeffs()
148 u32 *sc_reg17, unsigned int src_w, unsigned int src_h, in sc_config_scaler() argument
178 if (src_w == dst_w && src_h == dst_h) { in sc_config_scaler()
213 if (dst_h < (src_h >> 2)) { in sc_config_scaler()
222 factor = (u16) ((dst_h << 10) / src_h); in sc_config_scaler()
238 src_h, dst_h, factor, row_acc_init_rav, in sc_config_scaler()
242 row_acc_inc = ((src_h - 1) << 16) / (dst_h - 1); in sc_config_scaler()
[all …]
/drivers/media/pci/ivtv/
Divtv-yuv.c41 y_decode_height = uv_decode_height = f->src_h + f->src_y; in ivtv_yuv_prep_user_dma()
395 f->tru_h, f->src_h, f->dst_h, f->src_y, f->dst_y); in ivtv_yuv_handle_vertical()
425 reg_2918 = (f->dst_h << 16) | (f->src_h + src_minor_y); in ivtv_yuv_handle_vertical()
427 reg_2918 = (f->dst_h << 16) | ((f->src_h + src_minor_y) << 1); in ivtv_yuv_handle_vertical()
430 reg_291c = (f->dst_h << 16) | ((f->src_h + src_minor_uv) >> 1); in ivtv_yuv_handle_vertical()
432 reg_291c = (f->dst_h << 16) | (f->src_h + src_minor_uv); in ivtv_yuv_handle_vertical()
434 reg_2964_base = (src_minor_y * ((f->dst_h << 16) / f->src_h)) >> 14; in ivtv_yuv_handle_vertical()
435 reg_2968_base = (src_minor_uv * ((f->dst_h << 16) / f->src_h)) >> 14; in ivtv_yuv_handle_vertical()
437 if (f->dst_h / 2 >= f->src_h && !f->interlaced_y) { in ivtv_yuv_handle_vertical()
438 master_height = (f->src_h * 0x00400000) / f->dst_h; in ivtv_yuv_handle_vertical()
[all …]
/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4_plane.c51 uint32_t src_w, uint32_t src_h);
125 state->src_w, state->src_h); in mdp4_plane_atomic_update()
197 uint32_t src_w, uint32_t src_h) in mdp4_plane_mode_set() argument
220 src_h = src_h >> 16; in mdp4_plane_mode_set()
223 fb->base.id, src_x, src_y, src_w, src_h, in mdp4_plane_mode_set()
233 if (src_h > (crtc_h * DOWN_SCALE_MAX)) { in mdp4_plane_mode_set()
243 if (crtc_h > (src_h * UP_SCALE_MAX)) { in mdp4_plane_mode_set()
264 if (src_h != crtc_h) { in mdp4_plane_mode_set()
270 if (crtc_h > src_h) in mdp4_plane_mode_set()
272 else if (crtc_h <= (src_h / 4)) in mdp4_plane_mode_set()
[all …]
/drivers/gpu/drm/zte/
Dzx_plane.c148 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h) in zx_vl_rsz_setup() argument
152 u32 src_chroma_h = src_h; in zx_vl_rsz_setup()
156 zx_writel(rsz + RSZ_SRC_CFG, RSZ_VER(src_h - 1) | RSZ_HOR(src_w - 1)); in zx_vl_rsz_setup()
167 src_chroma_h = src_h >> 1; in zx_vl_rsz_setup()
174 zx_writel(rsz + RSZ_VL_LUMA_VER, rsz_step_value(src_h, dst_h)); in zx_vl_rsz_setup()
194 u32 src_x, src_y, src_w, src_h; in zx_vl_plane_atomic_update() local
208 src_h = drm_rect_height(src) >> 16; in zx_vl_plane_atomic_update()
227 zx_writel(layer + VL_SRC_SIZE, GL_SRC_W(src_w) | GL_SRC_H(src_h)); in zx_vl_plane_atomic_update()
249 zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h); in zx_vl_plane_atomic_update()
338 static void zx_gl_rsz_setup(struct zx_plane *zplane, u32 src_w, u32 src_h, in zx_gl_rsz_setup() argument
[all …]
/drivers/gpu/drm/armada/
Darmada_trace.h34 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h),
35 TP_ARGS(plane, crtc, fb, crtc_x, crtc_y, crtc_w, crtc_h, src_x, src_y, src_w, src_h),
47 __field(u32, src_h)
60 __entry->src_h = src_h;
67 __entry->src_w >> 16, __entry->src_h >> 16)
/drivers/gpu/drm/sti/
Dsti_hqvdp.c480 int src_w, src_h, dst_w, dst_h; in hqvdp_dbg_dump_cmd() local
513 src_h = c->top.input_viewport_size >> 16; in hqvdp_dbg_dump_cmd()
514 seq_printf(s, "\t%dx%d", src_w, src_h); in hqvdp_dbg_dump_cmd()
540 if (dst_h > src_h) in hqvdp_dbg_dump_cmd()
541 seq_printf(s, " %d/1", dst_h / src_h); in hqvdp_dbg_dump_cmd()
543 seq_printf(s, " 1/%d", src_h / dst_h); in hqvdp_dbg_dump_cmd()
734 int src_w, int src_h, in sti_hqvdp_check_hw_scaling() argument
743 inv_zy = DIV_ROUND_UP(src_h, dst_h); in sti_hqvdp_check_hw_scaling()
1029 int src_x, src_y, src_w, src_h; in sti_hqvdp_atomic_check() local
1045 src_h = state->src_h >> 16; in sti_hqvdp_atomic_check()
[all …]
Dsti_cursor.c193 int src_w, src_h; in sti_cursor_atomic_check() local
207 src_h = state->src_h >> 16; in sti_cursor_atomic_check()
210 src_h < STI_CURS_MIN_SIZE || in sti_cursor_atomic_check()
212 src_h > STI_CURS_MAX_SIZE) { in sti_cursor_atomic_check()
214 src_w, src_h); in sti_cursor_atomic_check()
221 (cursor->height != src_h)) { in sti_cursor_atomic_check()
223 cursor->height = src_h; in sti_cursor_atomic_check()
Dsti_gdp.c627 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_check() local
645 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); in sti_gdp_atomic_check()
691 src_w, src_h, src_x, src_y); in sti_gdp_atomic_check()
706 int src_x, src_y, src_w, src_h; in sti_gdp_atomic_update() local
728 (oldstate->src_h == state->src_h)) { in sti_gdp_atomic_update()
754 src_h = clamp_val(state->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT); in sti_gdp_atomic_update()
785 dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h); in sti_gdp_atomic_update()
796 top_field->gam_gdp_size = src_h << 16 | src_w; in sti_gdp_atomic_update()
/drivers/gpu/drm/nouveau/dispnv04/
Doverlay.c93 uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h, in verify_scaling() argument
96 if (crtc_w < (src_w >> shift) || crtc_h < (src_h >> shift)) { in verify_scaling()
98 src_w, src_h, crtc_w, crtc_h); in verify_scaling()
116 uint32_t src_w, uint32_t src_h, in nv10_update_plane() argument
137 src_h >>= 16; in nv10_update_plane()
139 ret = verify_scaling(fb, shift, 0, 0, src_w, src_h, crtc_w, crtc_h); in nv10_update_plane()
154 nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); in nv10_update_plane()
157 nvif_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h); in nv10_update_plane()
365 uint32_t src_w, uint32_t src_h, in nv04_update_plane() argument
381 src_h >>= 16; in nv04_update_plane()
[all …]
/drivers/gpu/drm/sun4i/
Dsun8i_vi_layer.c74 u32 src_w, src_h, dst_w, dst_h; in sun8i_vi_layer_update_coord() local
89 src_h = drm_rect_height(&state->src) >> 16; in sun8i_vi_layer_update_coord()
111 src_h = (src_h + remainder) & ~mask; in sun8i_vi_layer_update_coord()
115 insize = SUN8I_MIXER_SIZE(src_w, src_h); in sun8i_vi_layer_update_coord()
122 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); in sun8i_vi_layer_update_coord()
151 required = src_h * 100 / dst_h; in sun8i_vi_layer_update_coord()
155 vm = src_h; in sun8i_vi_layer_update_coord()
157 src_h = vn; in sun8i_vi_layer_update_coord()
171 vscale = (src_h << 16) / dst_h; in sun8i_vi_layer_update_coord()
173 sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w, in sun8i_vi_layer_update_coord()
Dsun8i_ui_layer.c80 u32 src_w, src_h, dst_w, dst_h; in sun8i_ui_layer_update_coord() local
92 src_h = drm_rect_height(&state->src) >> 16; in sun8i_ui_layer_update_coord()
99 insize = SUN8I_MIXER_SIZE(src_w, src_h); in sun8i_ui_layer_update_coord()
135 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); in sun8i_ui_layer_update_coord()
149 vscale = state->src_h / state->crtc_h; in sun8i_ui_layer_update_coord()
151 sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w, in sun8i_ui_layer_update_coord()
Dsun8i_vi_scaler.c927 u32 src_w, u32 src_h, u32 dst_w, u32 dst_h, in sun8i_vi_scaler_setup() argument
942 insize = SUN8I_VI_SCALER_SIZE(src_w, src_h); in sun8i_vi_scaler_setup()
986 src_h / format->vsub)); in sun8i_vi_scaler_setup()
/drivers/media/platform/rockchip/rga/
Drga-hw.c166 unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y; in rga_cmd_set_trans_info() local
180 src_h = ctx->in.crop.height; in rga_cmd_set_trans_info()
259 if (dst_w == src_h) in rga_cmd_set_trans_info()
260 src_h -= 8; in rga_cmd_set_trans_info()
285 if (src_h == scale_dst_h) { in rga_cmd_set_trans_info()
288 } else if (src_h > scale_dst_h) { in rga_cmd_set_trans_info()
291 rga_get_scaling(src_h, scale_dst_h) + 1; in rga_cmd_set_trans_info()
295 rga_get_scaling(src_h - 1, scale_dst_h - 1); in rga_cmd_set_trans_info()
305 src_act_info.data.act_height = src_h - 1; in rga_cmd_set_trans_info()
316 src_w, src_h); in rga_cmd_set_trans_info()
/drivers/gpu/drm/atmel-hlcdc/
Datmel_hlcdc_plane.c53 uint32_t src_h; member
292 if (state->crtc_w == state->src_w && state->crtc_h == state->src_h) { in atmel_hlcdc_plane_setup_scaler()
303 yfactor = atmel_hlcdc_plane_phiscaler_get_factor(state->src_h, in atmel_hlcdc_plane_setup_scaler()
315 state->crtc_h < state->src_h ? in atmel_hlcdc_plane_setup_scaler()
322 yfactor = (1024 * state->src_h) / state->crtc_h; in atmel_hlcdc_plane_setup_scaler()
346 state->src_h)); in atmel_hlcdc_plane_update_pos_and_size()
499 pixels = (plane_state->src_w * plane_state->src_h) - in atmel_hlcdc_plane_prepare_ahb_routing()
623 state->src_h = drm_rect_height(&s->src); in atmel_hlcdc_plane_atomic_check()
629 if ((state->src_x | state->src_y | state->src_w | state->src_h) & in atmel_hlcdc_plane_atomic_check()
636 state->src_h >>= 16; in atmel_hlcdc_plane_atomic_check()
[all …]
/drivers/gpu/drm/arm/
Dmalidp_planes.c276 u32 src_w, src_h; in malidp_se_check_scaling() local
290 src_w = state->src_h >> 16; in malidp_se_check_scaling()
291 src_h = state->src_w >> 16; in malidp_se_check_scaling()
294 src_h = state->src_h >> 16; in malidp_se_check_scaling()
297 if ((state->crtc_w == src_w) && (state->crtc_h == src_h)) { in malidp_se_check_scaling()
752 u32 src_w, src_h, val = 0, src_x, src_y; in malidp_de_set_plane_afbc() local
768 src_h = plane->state->src_h >> 16; in malidp_de_set_plane_afbc()
777 val = ((fb->height - (src_y + src_h)) << MALIDP_AD_CROP_BOTTOM_OFFSET) | in malidp_de_set_plane_afbc()
799 u32 src_w, src_h, dest_w, dest_h, val; in malidp_de_plane_update() local
811 src_h = fb->height; in malidp_de_plane_update()
[all …]
/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_plane.c275 if (state->src_h > max_height) in mdp5_plane_atomic_check_with_state()
318 ((state->src_h >> 16) != state->crtc_h)) in mdp5_plane_atomic_check_with_state()
465 plane->state->src_h != state->src_h || in mdp5_plane_atomic_async_check()
747 uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) in mdp5_write_pixel_ext() argument
755 uint32_t roi_h = src_h; in mdp5_write_pixel_ext()
827 u32 src_w, u32 src_h) in mdp5_hwpipe_mode_set() argument
840 MDP5_PIPE_SRC_SIZE_HEIGHT(src_h)); in mdp5_hwpipe_mode_set()
884 src_h, pe->top, pe->bottom); in mdp5_hwpipe_mode_set()
933 uint32_t src_w, src_h; in mdp5_plane_mode_set() local
949 src_h = drm_rect_height(src); in mdp5_plane_mode_set()
[all …]
/drivers/gpu/drm/
Ddrm_plane.c602 uint32_t src_w, uint32_t src_h) in __setplane_check() argument
635 ret = drm_framebuffer_check_src_coords(src_x, src_y, src_w, src_h, fb); in __setplane_check()
680 uint32_t src_w, uint32_t src_h, in __setplane_internal() argument
702 src_x, src_y, src_w, src_h); in __setplane_internal()
709 src_x, src_y, src_w, src_h, ctx); in __setplane_internal()
732 uint32_t src_w, uint32_t src_h, in __setplane_atomic() argument
752 src_x, src_y, src_w, src_h); in __setplane_atomic()
758 src_x, src_y, src_w, src_h, ctx); in __setplane_atomic()
768 uint32_t src_w, uint32_t src_h) in setplane_internal() argument
779 src_x, src_y, src_w, src_h, &ctx); in setplane_internal()
[all …]
Ddrm_plane_helper.c120 .src_h = drm_rect_height(src), in drm_plane_helper_check_update()
154 uint32_t src_w, uint32_t src_h, in drm_primary_helper_update() argument
168 .y2 = src_y + src_h, in drm_primary_helper_update()
/drivers/gpu/drm/selftests/
Dtest-drm_plane_helper.c16 unsigned src_w, unsigned src_h) in set_src() argument
21 plane_state->src_h = src_h; in set_src()
26 unsigned src_w, unsigned src_h) in check_src_eq() argument
42 drm_rect_height(&plane_state->src) != src_h) { in check_src_eq()
/drivers/gpu/drm/meson/
Dmeson_plane.c115 int src_w, src_h, dst_w, dst_h; in meson_plane_atomic_update() local
200 src_h = fixed16_to_int(state->src_h); in meson_plane_atomic_update()
218 vf_phase_step = (src_h << 20) / dst_h; in meson_plane_atomic_update()
228 if (src_h != dst_h || src_w != dst_w) { in meson_plane_atomic_update()
230 SCI_WH_M1_H(src_h - 1); in meson_plane_atomic_update()
245 if (src_h != dst_h) { in meson_plane_atomic_update()
/drivers/gpu/drm/vc4/
Dvc4_plane.c345 vc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16; in vc4_plane_setup_clipping_and_scaling()
358 vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0], in vc4_plane_setup_clipping_and_scaling()
368 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample; in vc4_plane_setup_clipping_and_scaling()
374 vc4_get_scaling_mode(vc4_state->src_h[1], in vc4_plane_setup_clipping_and_scaling()
470 vc4_state->src_h[channel], vc4_state->crtc_h); in vc4_write_scaling_parameters()
483 vc4_state->src_h[channel], vc4_state->crtc_h); in vc4_write_scaling_parameters()
530 vscale_factor = DIV_ROUND_UP(vc4_state->src_h[i], in vc4_plane_calc_load()
533 vc4_state->src_h[i] * vscale_factor * in vc4_plane_calc_load()
632 src_y += vc4_state->src_h[0] - 1; in vc4_plane_mode_set()
825 VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT)); in vc4_plane_mode_set()
[all …]
/drivers/gpu/drm/arm/display/komeda/
Dkomeda_framebuffer.c209 u32 src_x, u32 src_y, u32 src_w, u32 src_h) in komeda_fb_check_src_coords() argument
216 if ((src_x + src_w > fb->width) || (src_y + src_h > fb->height)) { in komeda_fb_check_src_coords()
222 (src_y % info->vsub) || (src_h % info->vsub)) { in komeda_fb_check_src_coords()
224 src_x, src_y, src_w, src_h, info->format); in komeda_fb_check_src_coords()
229 (src_y % block_h) || (src_h % block_h)) { in komeda_fb_check_src_coords()
231 src_x, src_y, src_w, src_h, info->format); in komeda_fb_check_src_coords()
/drivers/gpu/drm/exynos/
Dexynos_drm_plane.c65 unsigned int src_w, src_h; in exynos_plane_mode_set() local
83 src_h = state->src_h >> 16; in exynos_plane_mode_set()
87 exynos_state->v_ratio = (src_h << 16) / crtc_h; in exynos_plane_mode_set()
/drivers/gpu/drm/i915/display/
Dintel_sprite.c289 u32 src_x, src_y, src_w, src_h, hsub, vsub; in intel_plane_check_src_coordinates() local
301 src_h = drm_rect_height(src) >> 16; in intel_plane_check_src_coordinates()
306 src->y2 = (src_y + src_h) << 16; in intel_plane_check_src_coordinates()
325 if (src_y % vsub || src_h % vsub) { in intel_plane_check_src_coordinates()
327 src_y, src_h, vsub, rotated ? "rotated " : ""); in intel_plane_check_src_coordinates()
556 u32 src_h = drm_rect_height(&plane_state->base.src) >> 16; in skl_program_plane() local
572 src_h--; in skl_program_plane()
590 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); in skl_program_plane()
1164 u32 src_h = drm_rect_height(&plane_state->base.src) >> 16; in ivb_update_plane() local
1172 src_h--; in ivb_update_plane()
[all …]
/drivers/gpu/drm/virtio/
Dvirtgpu_plane.c161 cpu_to_le32(plane->state->src_h >> 16), in virtio_gpu_primary_plane_update()
173 plane->state->src_h >> 16, in virtio_gpu_primary_plane_update()
178 plane->state->src_h >> 16, in virtio_gpu_primary_plane_update()
186 plane->state->src_h >> 16); in virtio_gpu_primary_plane_update()

1234