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Searched refs:tf_mask (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
139 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
141 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
234 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
236 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
281 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
283 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
285 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
287 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
290 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
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Ddcn10_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
510 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) in dpp1_dppclk_control()
567 const struct dcn_dpp_mask *tf_mask) in dpp1_construct() argument
577 dpp->tf_mask = tf_mask; in dpp1_construct()
Ddcn10_dpp_dscl.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
384 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, in dpp1_dscl_set_scl_filter()
Ddcn10_resource.c395 static const struct dcn_dpp_mask tf_mask = { variable
596 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
Ddcn10_dpp.h1349 const struct dcn_dpp_mask *tf_mask; member
1512 const struct dcn_dpp_mask *tf_mask);
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp_cm.c44 dpp->tf_shift->field_name, dpp->tf_mask->field_name
211 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
213 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
215 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
217 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
220 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
222 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
224 reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
226 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
228 reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B; in dcn20_dpp_cm_get_reg_field()
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Ddcn20_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
500 const struct dcn2_dpp_mask *tf_mask) in dpp2_construct() argument
510 dpp->tf_mask = tf_mask; in dpp2_construct()
Ddcn20_dpp.h631 const struct dcn2_dpp_mask *tf_mask; member
704 const struct dcn2_dpp_mask *tf_mask);
Ddcn20_resource.c587 static const struct dcn2_dpp_mask tf_mask = { variable
872 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn20_dpp_create()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c614 static const struct dcn2_dpp_mask tf_mask = { variable
666 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()