Home
last modified time | relevance | path

Searched refs:tf_regs (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp.c42 dpp->tf_regs->reg
498 const struct dcn2_dpp_registers *tf_regs, in dpp2_construct() argument
508 dpp->tf_regs = tf_regs; in dpp2_construct()
Ddcn20_resource.c569 #define tf_regs(id)\ macro
574 static const struct dcn2_dpp_registers tf_regs[] = { variable
575 tf_regs(0),
576 tf_regs(1),
577 tf_regs(2),
578 tf_regs(3),
579 tf_regs(4),
580 tf_regs(5),
872 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn20_dpp_create()
Ddcn20_dpp.h629 const struct dcn2_dpp_registers *tf_regs; member
702 const struct dcn2_dpp_registers *tf_regs,
Ddcn20_dpp_cm.c37 dpp->tf_regs->reg
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp.c42 dpp->tf_regs->reg
565 const struct dcn_dpp_registers *tf_regs, in dpp1_construct() argument
575 dpp->tf_regs = tf_regs; in dpp1_construct()
Ddcn10_resource.c377 #define tf_regs(id)\ macro
382 static const struct dcn_dpp_registers tf_regs[] = { variable
383 tf_regs(0),
384 tf_regs(1),
385 tf_regs(2),
386 tf_regs(3),
596 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
Ddcn10_dpp_dscl.c43 dpp->tf_regs->reg
Ddcn10_dpp_cm.c43 dpp->tf_regs->reg
Ddcn10_dpp.h1347 const struct dcn_dpp_registers *tf_regs; member
1510 const struct dcn_dpp_registers *tf_regs,
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c598 #define tf_regs(id)\ macro
603 static const struct dcn2_dpp_registers tf_regs[] = { variable
604 tf_regs(0),
605 tf_regs(1),
606 tf_regs(2),
607 tf_regs(3),
666 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()