Home
last modified time | relevance | path

Searched refs:ulv (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/radeon/
Dsi_dpm.c4635 struct si_ulv_param *ulv = &si_pi->ulv; in si_populate_ulv_state() local
4639 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, in si_populate_ulv_state()
4648 if (ulv->one_pcie_lane_in_ulv) in si_populate_ulv_state()
4664 struct si_ulv_param *ulv = &si_pi->ulv; in si_program_ulv_memory_timing_parameters() local
4668 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, in si_program_ulv_memory_timing_parameters()
4674 ulv->volt_change_delay); in si_program_ulv_memory_timing_parameters()
4699 const struct si_ulv_param *ulv = &si_pi->ulv; in si_init_smc_table() local
4759 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
4768 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); in si_init_smc_table()
4769 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); in si_init_smc_table()
[all …]
Dbtc_dpm.c1391 if (eg_pi->ulv.supported) { in btc_disable_ulv()
1403 struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; in btc_populate_ulv_state()
1677 if (eg_pi->ulv.supported) { in btc_init_smc_table()
1680 eg_pi->ulv.supported = false; in btc_init_smc_table()
1788 if (eg_pi->ulv.supported) in btc_set_boot_state_timing()
1797 struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; in btc_is_state_ulv_compatible()
1815 struct rv7xx_pl *ulv_pl = eg_pi->ulv.pl; in btc_set_ulv_dram_timing()
1844 if (eg_pi->ulv.supported) { in btc_set_power_state_conditionally_enable_ulv()
2568 eg_pi->ulv.supported = false; in btc_dpm_init()
Dcypress_dpm.h87 struct evergreen_ulv_param ulv; member
Dsi_dpm.h160 struct si_ulv_param ulv; member
Dci_dpm.h232 struct ci_ulv_parm ulv; member
Dci_dpm.c3108 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv() local
3110 if (ulv->supported) { in ci_enable_ulv()
3132 pi->ulv.supported = false; in ci_populate_ulv_level()
3558 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table() local
3581 if (ulv->supported) { in ci_init_smc_table()
3585 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); in ci_init_smc_table()
5502 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5503 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5504 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
Drv770_dpm.c2236 eg_pi->ulv.supported = true; in rv7xx_parse_pplib_clock_info()
2237 eg_pi->ulv.pl = pl; in rv7xx_parse_pplib_clock_info()
Dni_dpm.c3956 eg_pi->ulv.supported = true; in ni_parse_pplib_clock_info()
3957 eg_pi->ulv.pl = pl; in ni_parse_pplib_clock_info()
4063 eg_pi->ulv.supported = false; in ni_dpm_init()
Dcypress_dpm.c2037 eg_pi->ulv.supported = false; in cypress_dpm_init()
/drivers/gpu/drm/amd/amdgpu/
Dsi_dpm.c5098 struct si_ulv_param *ulv = &si_pi->ulv; in si_populate_ulv_state() local
5102 ret = si_convert_power_level_to_smc(adev, &ulv->pl, in si_populate_ulv_state()
5111 if (ulv->one_pcie_lane_in_ulv) in si_populate_ulv_state()
5127 struct si_ulv_param *ulv = &si_pi->ulv; in si_program_ulv_memory_timing_parameters() local
5131 ret = si_populate_memory_timing_parameters(adev, &ulv->pl, in si_program_ulv_memory_timing_parameters()
5137 ulv->volt_change_delay); in si_program_ulv_memory_timing_parameters()
5161 const struct si_ulv_param *ulv = &si_pi->ulv; in si_init_smc_table() local
5221 if (ulv->supported && ulv->pl.vddc) { in si_init_smc_table()
5230 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); in si_init_smc_table()
5231 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); in si_init_smc_table()
[all …]
Dsi_dpm.h671 struct evergreen_ulv_param ulv; member
967 struct si_ulv_param ulv; member