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Searched refs:v_total (Results 1 – 25 of 43) sorted by relevance

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/drivers/gpu/drm/amd/display/modules/freesync/
Dfreesync.c111 unsigned int v_total) in calc_duration_in_us_from_v_total() argument
114 (unsigned int)(div64_u64(((unsigned long long)(v_total) in calc_duration_in_us_from_v_total()
125 unsigned int v_total = stream->timing.v_total; in calc_v_total_from_refresh() local
132 v_total = div64_u64(div64_u64(((unsigned long long)( in calc_v_total_from_refresh()
137 if (v_total < stream->timing.v_total) { in calc_v_total_from_refresh()
138 ASSERT(v_total < stream->timing.v_total); in calc_v_total_from_refresh()
139 v_total = stream->timing.v_total; in calc_v_total_from_refresh()
142 return v_total; in calc_v_total_from_refresh()
150 unsigned int v_total = 0; in calc_v_total_from_duration() local
158 v_total = div64_u64(div64_u64(((unsigned long long)( in calc_v_total_from_duration()
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/drivers/video/fbdev/matrox/
Dmatroxfb_g450.c234 unsigned int v_total; member
339 if (vtotal < outd->v_total) { in computeRegs()
340 unsigned int yovr = outd->v_total - vtotal; in computeRegs()
343 } else if (vtotal > outd->v_total) { in computeRegs()
344 vdisplay = outd->v_total - 4; in computeRegs()
345 vsyncend = outd->v_total; in computeRegs()
347 upper = (outd->v_total - vsyncend) >> 1; /* in field lines */ in computeRegs()
348 r->regs[0x17] = outd->v_total / 4; in computeRegs()
349 r->regs[0x18] = outd->v_total & 3; in computeRegs()
355 mt->VSyncStart = outd->v_total - 2; in computeRegs()
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/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_optc.c152 uint32_t v_total; in optc1_program_timing() local
201 v_total = patched_crtc_timing.v_total - 1; in optc1_program_timing()
204 OTG_V_TOTAL, v_total); in optc1_program_timing()
210 OTG_V_TOTAL_MAX, v_total); in optc1_program_timing()
212 OTG_V_TOTAL_MIN, v_total); in optc1_program_timing()
222 asic_blank_start = patched_crtc_timing.v_total - in optc1_program_timing()
310 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch; in optc1_set_vtg_params()
515 v_blank = (timing->v_total - timing->v_addressable - in optc1_validate_timing()
540 timing->v_total > optc1->max_v_total) in optc1_validate_timing()
1249 hw_crtc_timing.v_total = s.v_total + 1; in optc1_is_matching_timing()
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Ddcn10_opp.c309 uint32_t space1_size = timing->v_total - timing->v_addressable; in opp1_program_stereo()
311 uint32_t space2_size = timing->v_total - timing->v_addressable; in opp1_program_stereo()
Ddcn10_stream_encoder.c270 hw_crtc_timing.v_total /= 2; in enc1_stream_encoder_dp_set_stream_attribute()
432 DP_MSA_VTOTAL, hw_crtc_timing.v_total); in enc1_stream_encoder_dp_set_stream_attribute()
448 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - in enc1_stream_encoder_dp_set_stream_attribute()
/drivers/gpu/ipu-v3/
Dipu-di.c207 u32 v_total = sig->mode.vactive + sig->mode.vsync_len + in ipu_di_sync_config_interlaced() local
212 .run_count = v_total * 2 - 1, in ipu_di_sync_config_interlaced()
223 .run_count = v_total - 1, in ipu_di_sync_config_interlaced()
231 .run_count = v_total / 2, in ipu_di_sync_config_interlaced()
262 ipu_di_write(di, v_total / 2 - 1, DI_SCR_CONF); in ipu_di_sync_config_interlaced()
270 u32 v_total = sig->mode.vactive + sig->mode.vsync_len + in ipu_di_sync_config_noninterlaced() local
288 .run_count = v_total - 1, in ipu_di_sync_config_noninterlaced()
327 .run_count = v_total - 1, in ipu_di_sync_config_noninterlaced()
356 .run_count = v_total - 1, in ipu_di_sync_config_noninterlaced()
374 .run_count = v_total - 1, in ipu_di_sync_config_noninterlaced()
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/drivers/gpu/drm/bridge/
Dlt9611.c152 u32 v_total, v_act, vpw, vfp, vss; in lt9611_mipi_video_setup() local
155 v_total = mode->vtotal; in lt9611_mipi_video_setup()
169 regmap_write(lt9611->regmap, 0x0d, (u8)(v_total / 256)); in lt9611_mipi_video_setup()
170 regmap_write(lt9611->regmap, 0x0e, (u8)(v_total % 256)); in lt9611_mipi_video_setup()
294 u32 v_total, v_act, h_act_a, h_act_b, h_total_sysclk; in lt9611_video_check() local
316 v_total = temp << 8; in lt9611_video_check()
320 v_total = v_total + temp; in lt9611_video_check()
355 h_act_a, h_act_b, v_act, v_total, h_total_sysclk); in lt9611_video_check()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c101 uint32_t vertical_total_min = stream->timing.v_total; in dce110_get_min_vblank_time_us()
165 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) in dce110_fill_display_configs()
166 / stream->timing.v_total; in dce110_fill_display_configs()
/drivers/gpu/drm/radeon/
Dradeon_legacy_tv.c429 unsigned int h_total, v_total, f_total; in radeon_legacy_tv_init_restarts() local
440 v_total = const_ptr->ver_total; in radeon_legacy_tv_init_restarts()
486 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); in radeon_legacy_tv_init_restarts()
488 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); in radeon_legacy_tv_init_restarts()
497 tv_dac->tv.vrestart = restart % v_total; in radeon_legacy_tv_init_restarts()
498 restart /= v_total; in radeon_legacy_tv_init_restarts()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_mem_input.c526 uint32_t v_total, in get_dmif_switch_time_us() argument
538 if (!h_total || v_total || !pix_clk_khz) in get_dmif_switch_time_us()
543 pixels_per_frame = h_total * v_total; in get_dmif_switch_time_us()
573 uint32_t v_total, in dce_mi_allocate_dmif() argument
581 v_total, in dce_mi_allocate_dmif()
Ddce_clk_mgr.c537 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) in dce110_fill_display_configs()
538 / stream->timing.v_total; in dce110_fill_display_configs()
555 (stream->timing.v_total in dce110_get_min_vblank_time_us()
Ddce_stream_encoder.c297 hw_crtc_timing.v_total /= 2; in dce110_stream_encoder_dp_set_stream_attribute()
470 DP_MSA_VTOTAL, hw_crtc_timing.v_total); in dce110_stream_encoder_dp_set_stream_attribute()
487 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - in dce110_stream_encoder_dp_set_stream_attribute()
/drivers/video/fbdev/aty/
Daty128fb.c422 u32 v_total, v_sync_strt_wid; member
1029 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); in aty128_set_crtc()
1046 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; in aty128_var_to_crtc() local
1108 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; in aty128_var_to_crtc()
1111 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { in aty128_var_to_crtc()
1140 crtc->v_total = v_total | (v_disp << 16); in aty128_var_to_crtc()
1235 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; in aty128_crtc_to_var() local
1245 v_total = crtc->v_total & 0x7ff; in aty128_crtc_to_var()
1246 v_disp = (crtc->v_total >> 16) & 0x7ff; in aty128_crtc_to_var()
1259 upper = v_total - v_sync_strt - v_sync_wid; in aty128_crtc_to_var()
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Datyfb_base.c807 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync; in aty_var_to_crtc() local
885 v_total = v_sync_end + var->upper_margin; in aty_var_to_crtc()
963 v_total = v_disp + par->lcd_vblank_len / VScan; in aty_var_to_crtc()
984 v_total <<= 1; in aty_var_to_crtc()
990 v_total--; in aty_var_to_crtc()
998 FAIL_MAX("v_total too large", v_total, 0x7ff); in aty_var_to_crtc()
1017 crtc->v_tot_disp = v_total | (v_disp << 16); in aty_var_to_crtc()
1156 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; in aty_crtc_to_var() local
1167 v_total = crtc->v_tot_disp & 0x7ff; in aty_crtc_to_var()
1183 upper = v_total - v_sync_strt - v_sync_wid; in aty_crtc_to_var()
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/drivers/video/fbdev/nvidia/
Dnvidia.c314 int v_total = (info->var.yres + info->var.lower_margin + in nvidia_calc_regs() local
317 int v_blank_e = v_total + 1; in nvidia_calc_regs()
324 v_total |= 1; in nvidia_calc_regs()
327 v_start = v_total - 3; in nvidia_calc_regs()
328 v_end = v_total - 2; in nvidia_calc_regs()
343 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0); in nvidia_calc_regs()
344 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0) in nvidia_calc_regs()
349 | SetBitField(v_total, 9: 9, 5:5) in nvidia_calc_regs()
372 | SetBitField(v_total, 10: 10, 0:0); in nvidia_calc_regs()
379 state->extra = SetBitField(v_total, 11: 11, 0:0) in nvidia_calc_regs()
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_timing_generator.c108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
451 timing->v_total - 1); in dce120_timing_generator_program_blanking()
459 timing->v_total - 1); in dce120_timing_generator_program_blanking()
464 timing->v_total - 1); in dce120_timing_generator_program_blanking()
476 tmp1 = timing->v_total - (v_sync_start + timing->v_border_top); in dce120_timing_generator_program_blanking()
671 timing->v_total - timing->v_addressable - in dce120_timing_generator_enable_advanced_request()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_timing_generator.c313 bp_params.v_total = patched_crtc_timing.v_total; in dce110_timing_generator_program_timing_generator()
627 timing->v_total - 1, in dce110_timing_generator_program_blanking()
639 timing->v_total - 1, in dce110_timing_generator_program_blanking()
648 timing->v_total - 1, in dce110_timing_generator_program_blanking()
679 tmp = timing->v_total - (v_sync_start + timing->v_border_top); in dce110_timing_generator_program_blanking()
1141 timing->v_total > tg110->max_v_total) in dce110_timing_generator_validate_timing()
Ddce110_timing_generator_v.c272 timing->v_total - 1, in dce110_timing_generator_v_program_blanking()
303 tmp = timing->v_total - (v_sync_start + timing->v_border_top); in dce110_timing_generator_v_program_blanking()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dmem_input.h125 uint32_t v_total,/* for current target */
/drivers/gpu/drm/amd/display/include/
Dbios_parser_types.h171 uint32_t v_total; member
/drivers/gpu/drm/amd/display/dc/calcs/
Ddce_calcs.c246 data->v_total[0] = data->v_total[4]; in calculate_bandwidth()
248 data->v_total[1] = data->v_total[4]; in calculate_bandwidth()
251 data->v_total[2] = data->v_total[5]; in calculate_bandwidth()
253 data->v_total[3] = data->v_total[5]; in calculate_bandwidth()
384 data->v_total[maximum_number_of_surfaces - 2] = data->v_total[5]; in calculate_bandwidth()
385 data->v_total[maximum_number_of_surfaces - 1] = data->v_total[5]; in calculate_bandwidth()
1430 …peed_change_margin[k] = bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div… in calculate_bandwidth()
1434 …ange_margin[k] = bw_sub(bw_sub(bw_sub(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[k], bw_sub(bw_div… in calculate_bandwidth()
1992 …peed_change_latency_supported, bw_add(bw_sub(bw_div(bw_mul((bw_sub(data->v_total[i], bw_sub(bw_div… in calculate_bandwidth()
2797 data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); in populate_initial_data()
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Ddcn_calcs.c427 input->dest.vtotal = pipe->stream->timing.v_total; in pipe_ctx_to_e2e_pipe_params()
878 v->vtotal[input_idx] = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
881 v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total in dcn_validate_bandwidth()
1187 pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
1192 asic_blank_end = (pipe->stream->timing.v_total - in dcn_validate_bandwidth()
1228 hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; in dcn_validate_bandwidth()
/drivers/video/fbdev/mb862xx/
Dmb862xxfbdrv.c48 static inline int v_total(struct fb_var_screeninfo *var) in v_total() function
125 if (h_total(var) > 4096 || v_total(var) > 4096) in mb862xxfb_check_var()
259 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0)); in mb862xxfb_set_par()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_debug.c341 pipe_ctx->stream->timing.v_total, in context_timing_trace()
/drivers/gpu/drm/amd/display/dc/
Ddc_hw_types.h784 uint32_t v_total; member

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