Home
last modified time | relevance | path

Searched refs:vco (Results 1 – 25 of 40) sorted by relevance

12

/drivers/clk/spear/
Dclk-vco-pll.c97 for (*index = 0; *index < pll->vco->rtbl_cnt; (*index)++) { in clk_pll_round_rate_index()
100 *prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index, in clk_pll_round_rate_index()
131 if (pll->vco->lock) in clk_pll_recalc_rate()
132 spin_lock_irqsave(pll->vco->lock, flags); in clk_pll_recalc_rate()
134 p = readl_relaxed(pll->vco->cfg_reg); in clk_pll_recalc_rate()
136 if (pll->vco->lock) in clk_pll_recalc_rate()
137 spin_unlock_irqrestore(pll->vco->lock, flags); in clk_pll_recalc_rate()
148 struct pll_rate_tbl *rtbl = pll->vco->rtbl; in clk_pll_set_rate()
154 if (pll->vco->lock) in clk_pll_set_rate()
155 spin_lock_irqsave(pll->vco->lock, flags); in clk_pll_set_rate()
[all …]
DMakefile6 obj-y += clk.o clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
/drivers/clk/versatile/
Dclk-icst.c74 static int vco_get(struct clk_icst *icst, struct icst_vco *vco) in vco_get() argument
92 vco->v = val & INTEGRATOR_AP_CM_BITS; in vco_get()
93 vco->r = 22; in vco_get()
94 vco->s = 1; in vco_get()
107 vco->v = val & INTEGRATOR_AP_SYS_BITS; in vco_get()
108 vco->r = 46; in vco_get()
109 vco->s = 3; in vco_get()
124 vco->v = divxy ? 17 : 14; in vco_get()
125 vco->r = divxy ? 22 : 14; in vco_get()
126 vco->s = 1; in vco_get()
[all …]
Dicst.c27 unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco) in icst_hz() argument
29 u64 dividend = p->ref * 2 * (u64)(vco.v + 8); in icst_hz()
30 u32 divisor = (vco.r + 2) * p->s2div[vco.s]; in icst_hz()
49 struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max }; in icst_hz_to_vco() local
66 return vco; in icst_hz_to_vco()
68 vco.s = p->idx2s[i]; in icst_hz_to_vco()
91 vco.v = vd - 8; in icst_hz_to_vco()
92 vco.r = rd - 2; in icst_hz_to_vco()
99 return vco; in icst_hz_to_vco()
Dicst.h30 unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco);
/drivers/gpu/drm/i915/display/
Dintel_cdclk.c222 unsigned int vco; in intel_hpll_vco() local
242 vco = vco_table[tmp & 0x7]; in intel_hpll_vco()
243 if (vco == 0) in intel_hpll_vco()
246 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
248 return vco; in intel_hpll_vco()
263 cdclk_state->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
272 switch (cdclk_state->vco) { in g33_get_cdclk()
289 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, in g33_get_cdclk()
295 cdclk_state->vco, tmp); in g33_get_cdclk()
343 cdclk_state->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
[all …]
/drivers/clk/berlin/
Dberlin2-avpll.c115 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_is_enabled() local
118 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
119 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_is_enabled()
127 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_enable() local
130 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
131 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_enable()
135 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
142 struct berlin2_avpll_vco *vco = to_avpll_vco(hw); in berlin2_avpll_vco_disable() local
145 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable()
146 if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK) in berlin2_avpll_vco_disable()
[all …]
/drivers/clk/
Dclk-si544.c223 u64 vco; in si544_calc_muldiv() local
248 vco = FVCO_MIN + ls_freq - 1; in si544_calc_muldiv()
249 do_div(vco, ls_freq); in si544_calc_muldiv()
250 settings->hs_div = vco; in si544_calc_muldiv()
258 vco = (u64)ls_freq * settings->hs_div; in si544_calc_muldiv()
261 tmp = do_div(vco, FXO); in si544_calc_muldiv()
262 settings->fb_div_int = vco; in si544_calc_muldiv()
265 vco = (u64)tmp << 32; in si544_calc_muldiv()
266 vco += FXO / 2; /* Round to nearest multiple */ in si544_calc_muldiv()
267 do_div(vco, FXO); in si544_calc_muldiv()
[all …]
Dclk-stm32f4.c798 const struct stm32f4_vco_data *vco; in stm32f4_rcc_register_pll() local
805 vco = &vco_data[data->pll_num]; in stm32f4_rcc_register_pll()
807 init.name = vco->vco_name; in stm32f4_rcc_register_pll()
815 pll->gate.bit_idx = vco->bit_idx; in stm32f4_rcc_register_pll()
818 pll->offset = vco->offset; in stm32f4_rcc_register_pll()
820 pll->bit_rdy_idx = vco->bit_rdy_idx; in stm32f4_rcc_register_pll()
821 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1; in stm32f4_rcc_register_pll()
835 vco->vco_name, in stm32f4_rcc_register_pll()
/drivers/clk/pistachio/
Dclk-pll.c199 u64 val, vco, old_postdiv1, old_postdiv2; in pll_gf40lp_frac_set_rate() local
210 vco = params->fref; in pll_gf40lp_frac_set_rate()
211 vco *= (params->fbdiv << 24) + params->frac; in pll_gf40lp_frac_set_rate()
212 vco = div64_u64(vco, params->refdiv << 24); in pll_gf40lp_frac_set_rate()
214 if (vco < MIN_VCO_FRAC_FRAC || vco > MAX_VCO_FRAC_FRAC) in pll_gf40lp_frac_set_rate()
215 pr_warn("%s: VCO %llu is out of range %lu..%lu\n", name, vco, in pll_gf40lp_frac_set_rate()
222 if (val > vco / 16) in pll_gf40lp_frac_set_rate()
224 name, val, vco / 16); in pll_gf40lp_frac_set_rate()
356 u32 val, vco, old_postdiv1, old_postdiv2; in pll_gf40lp_laint_set_rate() local
366 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
[all …]
/drivers/clk/analogbits/
Dwrpll-cln28hpc.c225 u64 target_vco_rate, delta, best_delta, f_pre_div, vco, vco_pre; in wrpll_configure_for_rate() local
279 vco = vco_pre * f; in wrpll_configure_for_rate()
282 if (vco > target_vco_rate) { in wrpll_configure_for_rate()
284 vco = vco_pre * f; in wrpll_configure_for_rate()
285 } else if (vco < MIN_VCO_FREQ) { in wrpll_configure_for_rate()
287 vco = vco_pre * f; in wrpll_configure_for_rate()
290 delta = abs(target_rate - vco); in wrpll_configure_for_rate()
/drivers/video/fbdev/matrox/
Dg450_pll.c106 unsigned int *vco, unsigned int fout) in g450_firstpll() argument
114 *vco = vcomax; in g450_firstpll()
116 *vco = fout; in g450_firstpll()
131 *vco = tvco; in g450_firstpll()
133 return g450_nextpll(minfo, pi, vco, 0xFF0000 | p); in g450_firstpll()
440 unsigned int vco; in __g450_setclk() local
443 vco = g450_mnp2vco(minfo, mnp); in __g450_setclk()
448 if (vco < pixel_vco) { in __g450_setclk()
449 small = vco; in __g450_setclk()
453 big = vco; in __g450_setclk()
[all …]
/drivers/clk/bcm/
Dclk-iproc-pll.c287 struct iproc_pll_vco_param *vco) in pll_fractional_change_only() argument
303 if (ndiv_int != vco->ndiv_int) in pll_fractional_change_only()
309 if (pdiv != vco->pdiv) in pll_fractional_change_only()
315 static int pll_set_rate(struct iproc_clk *clk, struct iproc_pll_vco_param *vco, in pll_set_rate() argument
321 unsigned long rate = vco->rate; in pll_set_rate()
331 if (vco->pdiv == 0) in pll_set_rate()
334 ref_freq = parent_rate / vco->pdiv; in pll_set_rate()
364 if (pll_fractional_change_only(clk->pll, vco)) { in pll_set_rate()
370 val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; in pll_set_rate()
407 val |= vco->ndiv_int << ctrl->ndiv_int.shift; in pll_set_rate()
[all …]
/drivers/gpu/drm/gma500/
Dcdv_intel_display.c37 .vco = {.min = 1800000, .max = 3600000},
49 .vco = {.min = 1800000, .max = 3600000},
64 .vco = {.min = 1809000, .max = 3564000},
76 .vco = {.min = 1800000, .max = 3600000},
88 .vco = {.min = 1809000, .max = 3564000},
100 .vco = {.min = 1800000, .max = 3600000},
289 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
292 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
295 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
396 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
[all …]
Dgma_display.h25 int vco; member
40 struct gma_range_t dot, vco, n, m, m1, m2, p, p1; member
Dpsb_intel_display.c27 .vco = {.min = 1400000, .max = 2800000},
39 .vco = {.min = 1400000, .max = 2800000},
70 clock->vco = refclk * clock->m / (clock->n + 2); in psb_intel_clock()
71 clock->dot = clock->vco / clock->p; in psb_intel_clock()
Dgma_display.c687 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) in gma_pll_is_valid()
Doaktrail_hdmi.c104 struct intel_range vco, np, nr, nf; member
124 .vco = { .min = VCO_MIN, .max = VCO_MAX },
182 np_min = DIV_ROUND_UP(oaktrail_hdmi_limit.vco.min, target * 10); in oaktrail_hdmi_find_dpll()
183 np_max = oaktrail_hdmi_limit.vco.max / (target * 10); in oaktrail_hdmi_find_dpll()
/drivers/clk/mediatek/
Dclk-pll.c68 u64 vco; in __mtk_pll_recalc_rate() local
76 vco = (u64)fin * pcw; in __mtk_pll_recalc_rate()
78 if (pcwfbits && (vco & GENMASK(pcwfbits - 1, 0))) in __mtk_pll_recalc_rate()
81 vco >>= pcwfbits; in __mtk_pll_recalc_rate()
84 vco++; in __mtk_pll_recalc_rate()
86 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
/drivers/phy/rockchip/
Dphy-rockchip-inno-hdmi.c571 u64 vco; in inno_hdmi_phy_rk3228_clk_recalc_rate() local
577 vco = parent_rate * nf; in inno_hdmi_phy_rk3228_clk_recalc_rate()
580 do_div(vco, nd * 5); in inno_hdmi_phy_rk3228_clk_recalc_rate()
590 do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2)); in inno_hdmi_phy_rk3228_clk_recalc_rate()
593 inno->pixclock = vco; in inno_hdmi_phy_rk3228_clk_recalc_rate()
597 return vco; in inno_hdmi_phy_rk3228_clk_recalc_rate()
718 u64 vco; in inno_hdmi_phy_rk3328_clk_recalc_rate() local
724 vco = parent_rate * nf; in inno_hdmi_phy_rk3328_clk_recalc_rate()
730 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24)); in inno_hdmi_phy_rk3328_clk_recalc_rate()
734 do_div(vco, nd * 5); in inno_hdmi_phy_rk3328_clk_recalc_rate()
[all …]
/drivers/media/i2c/
Dmt9t112.c278 u32 vco, clk; in mt9t112_clock_info() local
307 vco = 2 * m * ext / (n + 1); in mt9t112_clock_info()
308 enable = ((vco < 384000) || (vco > 768000)) ? "X" : ""; in mt9t112_clock_info()
309 dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable); in mt9t112_clock_info()
311 clk = vco / (p1 + 1) / (p2 + 1); in mt9t112_clock_info()
315 clk = vco / (p3 + 1); in mt9t112_clock_info()
319 clk = vco / (p6 + 1); in mt9t112_clock_info()
323 clk = vco / (p5 + 1); in mt9t112_clock_info()
327 clk = vco / (p4 + 1); in mt9t112_clock_info()
331 clk = vco / (p7 + 1); in mt9t112_clock_info()
/drivers/media/tuners/
Dmax2165.c224 u8 vco, vco_sub_band, adc; in max2165_debug_status() local
236 vco = autotune >> 6; in max2165_debug_status()
246 dprintk("VCO: %d, VCO Sub-band: %d, ADC: %d\n", vco, vco_sub_band, adc); in max2165_debug_status()
/drivers/gpu/drm/msm/hdmi/
Dhdmi_phy_8996.c172 u64 vco, vco_optimal; in pll_get_post_div() local
185 vco = bclk >> half_rate_mode; in pll_get_post_div()
186 vco *= ratio_mult; in pll_get_post_div()
187 vco_freq[vco_freq_index++] = vco; in pll_get_post_div()
/drivers/iio/frequency/
Dadf4371.c207 static void adf4371_pll_fract_n_compute(unsigned long long vco, in adf4371_pll_fract_n_compute() argument
217 tmp = do_div(vco, pfd); in adf4371_pll_fract_n_compute()
221 *integer = vco; in adf4371_pll_fract_n_compute()
/drivers/media/dvb-frontends/
Dcx24120.c1237 u32 nxtal_khz, vco; in cx24120_set_vco() local
1242 vco = nxtal_khz * 10; in cx24120_set_vco()
1243 inv_vco = DIV_ROUND_CLOSEST_ULL(0x400000000ULL, vco); in cx24120_set_vco()
1246 xtal_khz, vco, inv_vco); in cx24120_set_vco()
1250 cmd.arg[0] = (vco >> 16) & 0xff; in cx24120_set_vco()
1251 cmd.arg[1] = (vco >> 8) & 0xff; in cx24120_set_vco()
1252 cmd.arg[2] = vco & 0xff; in cx24120_set_vco()

12