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Searched refs:video_div_table (Results 1 – 5 of 5) sorted by relevance

/drivers/clk/imx/
Dclk-imx6q.c109 static struct clk_div_table video_div_table[] = { variable
471 video_div_table[1].div = 1; in imx6q_clocks_init()
472 video_div_table[3].div = 1; in imx6q_clocks_init()
603 …_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_loc… in imx6q_clocks_init()
Dclk-imx6sll.c66 static const struct clk_div_table video_div_table[] = { variable
198 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
Dclk-imx6sl.c85 static const struct clk_div_table video_div_table[] = { variable
275 …iv", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_loc… in imx6sl_clocks_init()
Dclk-imx6ul.c89 static const struct clk_div_table video_div_table[] = { variable
225 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
Dclk-imx6sx.c102 static const struct clk_div_table video_div_table[] = { variable
261 CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); in imx6sx_clocks_init()