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Searched refs:vmw_read (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/vmwgfx/
Dvmwgfx_drv.c531 width = vmw_read(dev_priv, SVGA_REG_WIDTH); in vmw_get_initial_size()
532 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); in vmw_get_initial_size()
664 svga_id = vmw_read(dev_priv, SVGA_REG_ID); in vmw_driver_load()
671 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); in vmw_driver_load()
674 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); in vmw_driver_load()
684 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); in vmw_driver_load()
685 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); in vmw_driver_load()
686 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); in vmw_driver_load()
687 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); in vmw_driver_load()
693 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); in vmw_driver_load()
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Dvmwgfx_fifo.c56 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP); in vmw_fifo_have_3d()
122 DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH)); in vmw_fifo_init()
123 DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT)); in vmw_fifo_init()
124 DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL)); in vmw_fifo_init()
126 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_fifo_init()
127 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); in vmw_fifo_init()
128 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_fifo_init()
136 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS); in vmw_fifo_init()
183 while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) in vmw_fifo_release()
Dvmwgfx_kms.c1891 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) { in vmw_kms_write_svga()
1893 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH)); in vmw_kms_write_svga()
1905 vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH); in vmw_kms_save_vga()
1906 vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT); in vmw_kms_save_vga()
1907 vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL); in vmw_kms_save_vga()
1910 vmw_read(vmw_priv, SVGA_REG_PITCHLOCK); in vmw_kms_save_vga()
1918 vmw_priv->num_displays = vmw_read(vmw_priv, in vmw_kms_save_vga()
1927 save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY); in vmw_kms_save_vga()
1928 save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X); in vmw_kms_save_vga()
1929 save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y); in vmw_kms_save_vga()
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Dvmwgfx_ioctl.c168 (i, vmw_read(dev_priv, SVGA_REG_DEV_CAP)); in vmw_fill_compat_cap()
224 (i, vmw_read(dev_priv, SVGA_REG_DEV_CAP)); in vmw_get_cap_3d_ioctl()
Dvmwgfx_irq.c114 return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0); in vmw_fifo_idle()
Dvmwgfx_drv.h641 static inline uint32_t vmw_read(struct vmw_private *dev_priv, in vmw_read() function